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author | Andrey Petrov <anpetrov@fb.com> | 2020-03-30 12:25:06 -0700 |
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committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-04-04 04:27:45 +0000 |
commit | 8670e829a8f2f6e56c2405333a171c2bc7cd017b (patch) | |
tree | 11bde530ae6212446d31aad71ad7d79eeac5fa5e /src/soc/intel/xeon_sp/cpx/cpu.c | |
parent | ebda03ea5637cb2dd0b7426cbac72a4738ef7233 (diff) | |
download | coreboot-8670e829a8f2f6e56c2405333a171c2bc7cd017b.tar.xz |
soc/intel/xeon_sp/cpx: Add multi-core init
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks
and perform useful work. Tested on Cedar Island CRB with only 1
socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/cpu.c')
-rw-r--r-- | src/soc/intel/xeon_sp/cpx/cpu.c | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c new file mode 100644 index 0000000000..8824686674 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <arch/acpigen.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/mtrr.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/mp_init.h> +#include <soc/cpu.h> + +static const void *microcode_patch; + +void get_microcode_info(const void **microcode, int *parallel) +{ + *microcode = intel_mp_current_microcode(); + *parallel = 1; +} + +const void *intel_mp_current_microcode(void) +{ + return microcode_patch; +} + +static void each_cpu_init(struct device *cpu) +{ + printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); + + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = each_cpu_init, +}; + +static const struct cpu_device_id cpu_table[] = { + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +/* + * Do essential initialization tasks before APs can be fired up + */ +static void pre_mp_init(void) +{ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_thread_count(void) +{ + unsigned int num_phys = 0, num_virts = 0; + + cpu_read_topology(&num_phys, &num_virts); + printk(BIOS_SPEW, "Detected %u cores and %u threads\n", num_phys, num_virts); + return num_virts; +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_thread_count, + .get_microcode_info = get_microcode_info +}; + +void cpx_init_cpus(struct device *dev) +{ + microcode_patch = intel_microcode_find(); + + if (!microcode_patch) + printk(BIOS_ERR, "microcode not found in CBFS!\n"); + + intel_microcode_load_unlocked(microcode_patch); + + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); +} |