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author | Marc Jones <marcjones@sysproconsulting.com> | 2020-09-28 12:25:03 -0600 |
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committer | Marc Jones <marc@marcjonesconsulting.com> | 2020-10-06 15:19:08 +0000 |
commit | 70ddbd8ce18e5ea023e2cc5c5fb852f20e055d1d (patch) | |
tree | a931a153a19a809ac8aa5958b9bd2aa9df7d56b9 /src/soc/intel/xeon_sp/cpx/soc_acpi.c | |
parent | ccfaf253b5d76d4d23de871f47652721139a5558 (diff) | |
download | coreboot-70ddbd8ce18e5ea023e2cc5c5fb852f20e055d1d.tar.xz |
soc/intel/xeon_sp/cpx: Don't use SCI define
Continue preparations for common ACPI code.
Add code from skx and common/acpi to check the SCI register
instead of using a define.
Change-Id: I6b638d28775320894a6ab24ef486e67c181591eb
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45844
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/soc_acpi.c')
-rw-r--r-- | src/soc/intel/xeon_sp/cpx/soc_acpi.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index f48a666816..b0352d8567 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -42,6 +42,16 @@ int soc_madt_sci_irq_polarity(int sci) return MP_IRQ_POLARITY_HIGH; } +uint32_t soc_read_sci_irq_select(void) +{ + struct device *dev = PCH_DEV_PMC; + + if (!dev) + return 0; + + return pci_read_config32(dev, PMC_ACPI_CNT); +} + /* * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() * with a call from the common/function or find another way to call this at the correct place |