diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2020-03-16 22:46:57 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-03-26 02:06:45 +0000 |
| commit | 662da6cf7b181ea2787ba001d9cbb6d41916abec (patch) | |
| tree | 63a95b276913110c423c566db78b856650582ad3 /src/soc/intel/xeon_sp/include/soc/ramstage.h | |
| parent | a1b15172d7f0303e8a1fe147a778d73d4dc26b1a (diff) | |
| download | coreboot-662da6cf7b181ea2787ba001d9cbb6d41916abec.tar.xz | |
soc/intel/xeon_sp: Refactor code to allow for additional CPUs types
Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.
This is a preparation for future work that will enable next
generation server CPU.
TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/include/soc/ramstage.h')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/ramstage.h | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h deleted file mode 100644 index cf615ff635..0000000000 --- a/src/soc/intel/xeon_sp/include/soc/ramstage.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_RAMSTAGE_H_ -#define _SOC_RAMSTAGE_H_ - -#include <device/device.h> -#include <fsp/api.h> -#include <fsp/util.h> -#include <memory_info.h> - -void xeon_sp_init_cpus(struct device *dev); -void mainboard_silicon_init_params(FSPS_UPD *params); - -extern struct pci_operations soc_pci_ops; - -#endif |