diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2020-01-16 11:16:45 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-06 08:19:59 +0000 |
| commit | 8f89549d3c7d41643337662947cfdb2329bd030b (patch) | |
| tree | 81d337d1e0bc655d82f47ba8808f42713942dc6a /src/soc/intel/xeon_sp/include/soc/ramstage.h | |
| parent | e425a09d6a0016e128373941ee1cf223a528a0fc (diff) | |
| download | coreboot-8f89549d3c7d41643337662947cfdb2329bd030b.tar.xz | |
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable
Processor, which is a processor in Xeon-SP family. The code
is expected to be reusable for future geneations of Xeon-SP
processors, and will be updated with smaller targeted
patches accordingly, to add support for additional Xeon-SP
processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a
proof-of-concept build. The binary is not shared in public,
when this patch is upstreamed.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include/soc/ramstage.h')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/ramstage.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h new file mode 100644 index 0000000000..c012dd6cbd --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/ramstage.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include <device/device.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memory_info.h> + +void xeon_sp_init_cpus(struct device *dev); +void mainboard_silicon_init_params(FSPS_UPD *params); + +extern struct pci_operations soc_pci_ops; + +#endif |