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| author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-02-19 15:52:45 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 10:42:14 +0000 |
| commit | ebb7f54b1a107816e4f83bc31f1631acb85700d1 (patch) | |
| tree | 3568e691490943cc111b5ad590e0b74194a86a51 /src/soc/intel/xeon_sp/lpc.c | |
| parent | 3180af7fd6a86d202c241b02afa9cc4c0b9d9262 (diff) | |
| download | coreboot-ebb7f54b1a107816e4f83bc31f1631acb85700d1.tar.xz | |
soc/intel/xeon_sp: Enable LPC generic IO decode range
To use Intel common block LPC function that enables the IO ranges
defined in devicetree.cb.
Tested on OCP Tioga Pass with BMC LPC working.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38994
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/lpc.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/lpc.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 4dd6f7c657..6dc2c41fe0 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -16,8 +16,12 @@ #include <console/console.h> #include <arch/ioapic.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> #include <soc/soc_util.h> #include <soc/iomap.h> +#include <soc/pcr_ids.h> + +#include "chip.h" static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { { 0, 0 } @@ -28,6 +32,25 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) return xeon_lpc_fixed_mmio_ranges; } +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const config_t *config = config_of(dev); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) +{ + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); +} + void lpc_soc_init(struct device *dev) { printk(BIOS_SPEW, "pch: lpc_init\n"); |