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author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-12 21:17:56 +0100 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-20 10:18:46 +0000 |
commit | 3d802535cbf222d403e0d7d5cc6632546333a4c4 (patch) | |
tree | d81070cb4e983a44e790481e22d1746b699d0a22 /src/soc/intel/xeon_sp/pch.c | |
parent | 6e425e1275a7638eb4b42b4fdec23f5674d086f5 (diff) | |
download | coreboot-3d802535cbf222d403e0d7d5cc6632546333a4c4.tar.xz |
soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF
Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes
coreboot in control of these settings.
Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/pch.c')
-rw-r--r-- | src/soc/intel/xeon_sp/pch.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 2b35223d16..8de7743d94 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -5,7 +5,9 @@ #include <soc/pcr_ids.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <intelblocks/p2sb.h> #include <soc/bootblock.h> +#include <soc/pch.h> #include <soc/pmc.h> #include <console/console.h> @@ -51,3 +53,20 @@ void bootblock_pch_init(void) */ soc_config_acpibase(); } + +void override_hpet_ioapic_bdf(void) +{ + union p2sb_bdf ioapic_bdf = { + .bus = PCH_IOAPIC_BUS_NUMBER, + .dev = PCH_IOAPIC_DEV_NUM, + .fn = PCH_IOAPIC_FUNC_NUM, + }; + union p2sb_bdf hpet_bdf = { + .bus = HPET_BUS_NUM, + .dev = HPET_DEV_NUM, + .fn = HPET0_FUNC_NUM, + }; + + p2sb_set_ioapic_bdf(ioapic_bdf); + p2sb_set_hpet_bdf(hpet_bdf); +} |