diff options
author | Andrey Petrov <anpetrov@fb.com> | 2020-03-16 22:46:57 -0700 |
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committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-03-26 02:06:45 +0000 |
commit | 662da6cf7b181ea2787ba001d9cbb6d41916abec (patch) | |
tree | 63a95b276913110c423c566db78b856650582ad3 /src/soc/intel/xeon_sp/romstage.c | |
parent | a1b15172d7f0303e8a1fe147a778d73d4dc26b1a (diff) | |
download | coreboot-662da6cf7b181ea2787ba001d9cbb6d41916abec.tar.xz |
soc/intel/xeon_sp: Refactor code to allow for additional CPUs types
Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.
This is a preparation for future work that will enable next
generation server CPU.
TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/romstage.c')
-rw-r--r-- | src/soc/intel/xeon_sp/romstage.c | 28 |
1 files changed, 2 insertions, 26 deletions
diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index a519663134..9d3665c9fe 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -18,9 +18,9 @@ #include <intelblocks/rtc.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <fsp/util.h> #include <soc/romstage.h> -#include <soc/soc_util.h> -#include "chip.h" +#include <soc/util.h> asmlinkage void car_stage_entry(void) { @@ -55,27 +55,3 @@ asmlinkage void car_stage_entry(void) run_postcar_phase(&pcf); } - -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) -{ -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const config_t *config = config_of_soc(); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - - mupd->FspmUpdVersion = FSP_UPD_VERSION; - - // ErrorLevel - 0 (disable) to 8 (verbose) - m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; - m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; - - soc_memory_init_params(m_cfg); - - mainboard_memory_init_params(mupd); - - m_cfg->VTdConfig.VTdSupport = config->vtd_support; - m_cfg->VTdConfig.CoherencySupport = config->coherency_support; - m_cfg->VTdConfig.ATS = config->ats_support; -} |