diff options
author | Jonathan Zhang <jonzhang@fb.com> | 2020-01-16 11:16:45 -0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-06 08:19:59 +0000 |
commit | 8f89549d3c7d41643337662947cfdb2329bd030b (patch) | |
tree | 81d337d1e0bc655d82f47ba8808f42713942dc6a /src/soc/intel/xeon_sp/romstage.c | |
parent | e425a09d6a0016e128373941ee1cf223a528a0fc (diff) | |
download | coreboot-8f89549d3c7d41643337662947cfdb2329bd030b.tar.xz |
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable
Processor, which is a processor in Xeon-SP family. The code
is expected to be reusable for future geneations of Xeon-SP
processors, and will be updated with smaller targeted
patches accordingly, to add support for additional Xeon-SP
processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a
proof-of-concept build. The binary is not shared in public,
when this patch is upstreamed.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/romstage.c')
-rw-r--r-- | src/soc/intel/xeon_sp/romstage.c | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c new file mode 100644 index 0000000000..dc94dc6810 --- /dev/null +++ b/src/soc/intel/xeon_sp/romstage.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <intelblocks/rtc.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <soc/romstage.h> +#include <soc/soc_util.h> +#include "chip.h" + +asmlinkage void car_stage_entry(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + printk(BIOS_DEBUG, "FSP TempRamInit was successful...\n"); + + console_init(); + rtc_init(); + + fsp_memory_init(false); + printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n"); + + unlock_pam_regions(); + + if (postcar_frame_init(&pcf, 1 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t)cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram: 0x%lx\n", top_of_ram); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, + MTRR_TYPE_WRBACK); + + /* Cache the memory-mapped boot media. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + run_postcar_phase(&pcf); +} + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) +{ +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const config_t *config = config_of_soc(); + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + mupd->FspmUpdVersion = FSP_UPD_VERSION; + + // ErrorLevel - 0 (disable) to 8 (verbose) + m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; + m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; + + soc_memory_init_params(m_cfg); + + mainboard_memory_init_params(mupd); + + m_cfg->VTdConfig.VTdSupport = config->vtd_support; + m_cfg->VTdConfig.CoherencySupport = config->coherency_support; + m_cfg->VTdConfig.ATS = config->ats_support; +} |