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authorJohn Zhao <john.zhao@intel.com>2019-04-22 10:45:51 -0700
committerNico Huber <nico.h@gmx.de>2019-05-11 11:16:48 +0000
commit1159a163cd36318d27f8f3b71617ad4a5b781efb (patch)
tree05f00bfd909ae3fb52669596e9e5f23ab096bf8b /src/soc/intel
parent4249348735d18cb2d44506090a675a29b0567e7f (diff)
downloadcoreboot-1159a163cd36318d27f8f3b71617ad4a5b781efb.tar.xz
soc/intel/cnl: Enable VT-d
Enable VT-d through fsp upd VtdDisable. Update remapping structure types in numerical order as all remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. BUG=b:130351429 TEST=Booted to kernel and verified the DMAR table contents. Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/acpi.c15
-rw-r--r--src/soc/intel/cannonlake/chip.h3
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c5
-rw-r--r--src/soc/intel/cannonlake/systemagent.c6
4 files changed, 14 insertions, 15 deletions
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 209e7c52d4..ff9da451c8 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -304,13 +304,6 @@ static unsigned long soc_fill_dmar(unsigned long current)
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current);
-
- /* Add RMRR entry */
- tmp = current;
- current += acpi_create_dmar_rmrr(current, 0,
- sa_get_gsm_base(), sa_get_tolud_base() - 1);
- current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
- acpi_dmar_rmrr_fixup(tmp, current);
}
struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU);
@@ -344,6 +337,13 @@ static unsigned long soc_fill_dmar(unsigned long current)
acpi_dmar_drhd_fixup(tmp, current);
}
+ /* Add RMRR entry */
+ const unsigned long tmp = current;
+ current += acpi_create_dmar_rmrr(current, 0,
+ sa_get_gsm_base(), sa_get_tolud_base() - 1);
+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+ acpi_dmar_rmrr_fixup(tmp, current);
+
return current;
}
@@ -361,6 +361,7 @@ unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current,
printk(BIOS_DEBUG, "ACPI: * DMAR\n");
acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar);
+
current += dmar->header.length;
current = acpi_align_current(current);
acpi_add_table(rsdp, dmar);
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index f34528a017..2b2a51f6a0 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -344,9 +344,6 @@ struct soc_intel_cannonlake_config {
/* Enable Pch iSCLK */
uint8_t pch_isclk;
- /* Intel VT configuration */
- uint8_t VtdDisable;
-
/*
* Acoustic Noise Mitigation
* 0b - Disable
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index c71e4b551a..6e492bb73a 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -101,6 +101,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
assert(dev != NULL);
const config_t *config = dev->chip_info;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+ FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
soc_memory_init_params(m_cfg, config);
@@ -113,6 +114,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
/* Set debug probe type */
m_cfg->PlatformDebugConsent =
CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT;
+
+ /* Configure VT-d */
+ tconfig->VtdDisable = 0;
+
mainboard_memory_init_params(mupd);
}
diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c
index d850b15b34..3f01f14dcf 100644
--- a/src/soc/intel/cannonlake/systemagent.c
+++ b/src/soc/intel/cannonlake/systemagent.c
@@ -33,8 +33,6 @@
*/
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
- const struct soc_intel_cannonlake_config *const config = dev->chip_info;
-
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
"PCIEXBAR" },
@@ -63,10 +61,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
return;
- if (!(config && config->VtdDisable)) {
- sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
+ sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
ARRAY_SIZE(soc_vtd_resources));
- }
}
/*