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authorAngel Pons <th3fanbus@gmail.com>2020-10-13 23:37:07 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-10-23 20:29:07 +0000
commit162a73759901e0292bb7da593c31391bc0230bc0 (patch)
tree64a56d5f017e1a08404af3a9cb683c1838adee97 /src/soc/intel
parent973c9d45adc7f205a68c005083d21f2337616404 (diff)
downloadcoreboot-162a73759901e0292bb7da593c31391bc0230bc0.tar.xz
soc/intel/broadwell: Remove unnecessary array
The MAD_DIMM registers can be read within the loop just fine. Change-Id: Id0c79aaa506f7545826445bc5b065408105b46ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/broadwell/include/soc/systemagent.h3
-rw-r--r--src/soc/intel/broadwell/romstage/raminit.c7
2 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h
index 920b710d40..cc0dc4f0c5 100644
--- a/src/soc/intel/broadwell/include/soc/systemagent.h
+++ b/src/soc/intel/broadwell/include/soc/systemagent.h
@@ -87,6 +87,9 @@
#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x)))
#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x)))
+/* Memory controller characteristics */
+#define NUM_CHANNELS 2
+
#define MAD_CHNL 0x5000
#define MAD_DIMM(ch) (0x5004 + 4 * (ch))
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 4977b351f7..65e386a7c7 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -27,12 +27,9 @@
*/
static void report_memory_config(void)
{
- u32 addr_decode_ch[2];
int i;
const u32 addr_decoder_common = MCHBAR32(MAD_CHNL);
- addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0));
- addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1));
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
(MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
@@ -42,8 +39,8 @@ static void report_memory_config(void)
(addr_decoder_common >> 2) & 3,
(addr_decoder_common >> 4) & 3);
- for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
- u32 ch_conf = addr_decode_ch[i];
+ for (i = 0; i < NUM_CHANNELS; i++) {
+ const u32 ch_conf = MCHBAR32(MAD_DIMM(i));
printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);