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authorAaron Durbin <adurbin@chromium.org>2015-07-30 10:36:34 -0500
committerAaron Durbin <adurbin@chromium.org>2015-08-13 16:11:26 +0200
commit25477e03a117f3f420146ffde4b5c1eda9f5493b (patch)
tree2f0d8a9c6ea2f499b9d7422174b47d83c624316a /src/soc/intel
parentab454c6b71fd54b61cc90165fe801250890894d2 (diff)
downloadcoreboot-25477e03a117f3f420146ffde4b5c1eda9f5493b.tar.xz
skylake: fix garbled patch from upstream
In the review process for http://review.coreboot.org/#/c/11052/ the code was mangled and the result was unbuildable code. Fix this. BUG=chrome-os-partner:43419 BRANCH=None TEST=Can actually build bootblock. Original-Change-Id: I5bc63b8c435dbf025f1c334e9a1bc4a9da2b4902 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289788 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: Id0f67d8b74fa9146bf01990f599d538222f7e0e2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11167 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/bootblock/cpu.c25
1 files changed, 12 insertions, 13 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index 2e3e000aaa..6c5ab4fe6d 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -178,8 +178,16 @@ static void check_for_clean_reset(void)
soft_reset();
}
-static int need_microcode_update(void)
+static void patch_microcode(void)
{
+ const struct microcode *patch;
+ u32 current_rev;
+ msr_t msr;
+
+ patch = intel_microcode_find();
+
+ current_rev = read_microcode_rev();
+
/* If PRMRR/SGX is supported the FIT microcode load step will set
* msr 0x08b with the Patch revision id one less than the id in the
* microcode binary. The PRMRR support is indicated in the MSR
@@ -187,24 +195,15 @@ static int need_microcode_update(void)
* same microcode during early cpu initialization.
*/
msr = rdmsr(MTRRcap_MSR);
- return (msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1);
+ if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1))
+ intel_update_microcode_from_cbfs();
}
static void bootblock_cpu_init(void)
{
- const struct microcode *patch;
- u32 current_rev;
- msr_t msr;
-
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
check_for_clean_reset();
enable_rom_caching();
-
- patch = intel_microcode_find();
-
- current_rev = read_microcode_rev();
-
- if (need_microcode_update())
- intel_update_microcode_from_cbfs();
+ patch_microcode();
}