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authorDuncan Laurie <dlaurie@chromium.org>2017-02-17 17:16:43 -0800
committerMartin Roth <martinroth@google.com>2017-02-19 21:39:02 +0100
commit25c7d9342b8bdee61710a516440e4b9c4b83fb09 (patch)
tree2700558a829fd4b7a8f1cba15c6c0e21b69bbc27 /src/soc/intel
parentc9db384ea47b8b705ddeaf0319fd53b5c513f423 (diff)
downloadcoreboot-25c7d9342b8bdee61710a516440e4b9c4b83fb09.tar.xz
soc/intel/skylake: Disable s0ix if not enabled in devicetree
There is an enable_s0ix config option in the devicetree that should be used to disable it when not set: - do not export C8/C9/C10 C-states in _CST - do not enable SLP_S0 in FSP BUG=chrome-os-partner:58666 TEST=test on eve board to ensure that OS only sees 3 ACPI C-states instead of 6 and that it no longer attempts to enter C10 Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18394 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/acpi.c3
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c1
2 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 2f8cf51fac..4f2dafd9fd 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -146,9 +146,6 @@ static int cstate_set_non_s0ix[] = {
C_STATE_C1E,
C_STATE_C3,
C_STATE_C7S_LONG_LAT,
- C_STATE_C8,
- C_STATE_C9,
- C_STATE_C10
};
static int get_cores_per_package(void)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 9c87b65bbd..97a37e8afc 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -205,6 +205,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride;
params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
params->PchPmDeepSxPol = config->PmConfigDeepSxPol;
+ params->PchPmSlpS0Enable = config->s0ix_enable;
params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert;
params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert;