soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT

On tgl, we noticed system hang if a shutdown is triggered before fsps.
The dut is unable to shutdown properly due to tcss is stuck before
tcss_init in fsps.

This change enable power button smi on jsl, tgl, adl after fsps.
it can also prevent a shutdown failure due to lack of fsps init on
certain ip.

BUG=b:186194102, b:186815114
TEST=Power on the system and pressing power button repeatedly doesn't
     cause the system hang during shutdown.

Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

6 files changed, 38 insertions, 6 deletions

diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 6de1cb011c..b97521215e 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -99,10 +99,12 @@ static void post_mp_init(void)
 	cpu_set_max_ratio();
 
 	/*
-	 * Now that all APs have been relocated as well as the BSP let SMIs
+	 * 1. Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing.
+	 * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
+	 * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
 	 */
-	global_smi_enable();
+	global_smi_enable_no_pwrbtn();
 }
 
 static const struct mp_ops mp_ops = {
diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c
index e4c100933c..03399c312e 100644
--- a/src/soc/intel/alderlake/pmc.c
+++ b/src/soc/intel/alderlake/pmc.c
@@ -18,6 +18,7 @@
 #include <soc/pm.h>
 #include <soc/soc_chip.h>
 #include <stdint.h>
+#include <bootstate.h>
 
 #define PMC_HID		"INTC1026"
 
@@ -141,6 +142,14 @@ static void soc_acpi_mode_init(struct device *dev)
 	pmc_set_acpi_mode();
 }
 
+static void pm1_enable_pwrbtn_smi(void *unused)
+{
+	/* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */
+	pmc_update_pm1_enable(PWRBTN_EN);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
+
 struct device_operations pmc_ops = {
 	.read_resources	  = soc_pmc_read_resources,
 	.set_resources	  = noop_set_resources,
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 8e54eaa385..86077ff2d0 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -93,10 +93,12 @@ static void post_mp_init(void)
 	cpu_set_max_ratio();
 
 	/*
-	 * Now that all APs have been relocated as well as the BSP let SMIs
+	 * 1. Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing.
+	 * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
+	 * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
 	 */
-	global_smi_enable();
+	global_smi_enable_no_pwrbtn();
 }
 
 static const struct mp_ops mp_ops = {
diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c
index c0507d6f41..dce791c692 100644
--- a/src/soc/intel/jasperlake/pmc.c
+++ b/src/soc/intel/jasperlake/pmc.c
@@ -93,6 +93,14 @@ static void soc_acpi_mode_init(struct device *dev)
 	pmc_set_acpi_mode();
 }
 
+static void pm1_enable_pwrbtn_smi(void *unused)
+{
+	/* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */
+	pmc_update_pm1_enable(PWRBTN_EN);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
+
 struct device_operations pmc_ops = {
 	.read_resources		= soc_pmc_read_resources,
 	.set_resources		= noop_set_resources,
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index 925bddb56a..7bb9e611af 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -99,10 +99,12 @@ static void post_mp_init(void)
 	cpu_set_max_ratio();
 
 	/*
-	 * Now that all APs have been relocated as well as the BSP let SMIs
+	 * 1. Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing.
+	 * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
+	 * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
 	 */
-	global_smi_enable();
+	global_smi_enable_no_pwrbtn();
 }
 
 static const struct mp_ops mp_ops = {
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index c5a4ae526a..190f3ffddc 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -18,6 +18,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/soc_chip.h>
+#include <bootstate.h>
 
 #define PMC_HID		"INTC1026"
 
@@ -145,6 +146,14 @@ static void soc_acpi_mode_init(struct device *dev)
 	pmc_set_acpi_mode();
 }
 
+static void pm1_enable_pwrbtn_smi(void *unused)
+{
+	/* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */
+	pmc_update_pm1_enable(PWRBTN_EN);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
+
 struct device_operations pmc_ops = {
 	.read_resources	  = soc_pmc_read_resources,
 	.set_resources	  = noop_set_resources,