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authorAndrey Petrov <anpetrov@fb.com>2019-09-10 20:24:06 -0700
committerMartin Roth <martinroth@google.com>2019-09-21 20:38:10 +0000
commit3dd6867ea9374e442e8af000bada73c17631abb8 (patch)
tree2e5a5ac7ba08608a18f695ae0650a0516233ac03 /src/soc/intel
parentb18946a557b43f77904287187534d496c4b165a2 (diff)
downloadcoreboot-3dd6867ea9374e442e8af000bada73c17631abb8.tar.xz
soc/fsp_broadwell_de: Move function to get CPUBUSNO(1) into common file
Change-Id: I189eb8ffce2f0735ad9ba603b1d96786aa00fafb Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h1
-rw-r--r--src/soc/intel/fsp_broadwell_de/include/soc/vtd.h13
-rw-r--r--src/soc/intel/fsp_broadwell_de/romstage/romstage.c16
3 files changed, 19 insertions, 11 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
index 973f55983b..58591dcda0 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
@@ -32,6 +32,7 @@
#define VTD_FUNC 0
#define VTD_DEVID 0x6f28
#define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC)
+#define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC)
#define LPC_DEV 31
#define LPC_FUNC 0
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h b/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h
index 43da267dce..814cba02cd 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/vtd.h
@@ -16,6 +16,9 @@
#ifndef _BROADWELL_VTD_H_
#define _BROADWELL_VTD_H_
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+
#define VTD_CPUBUSNO 0x108
#define VTD_CPUBUSNO_BUS0_MASK 0xff
#define VTD_CPUBUSNO_BUS0_SHIFT 0
@@ -26,4 +29,14 @@
#define VTD_DFX1 0x804
#define VTD_DFX1_RANGE_3F8_DISABLE (1u << 29)
#define VTD_DFX1_RANGE_2F8_DISABLE (1u << 30)
+
+static inline uint8_t get_busno1(void)
+{
+ uint32_t reg32;
+
+ /* Figure out what bus number is assigned for CPUBUSNO(1) */
+ reg32 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_CPUBUSNO);
+ return ((reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK);
+}
+
#endif
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 5c9682ac9e..b0fad3f02b 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -61,24 +61,18 @@ static void setup_gpio_io_address(void)
static void enable_integrated_uart(uint8_t port)
{
- uint32_t reg32, busno1 = 0, ubox_uart_en = 0, dfx1 = 0;
- pci_devfn_t vtd_dev, ubox_dev;
-
- vtd_dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC);
-
- /* Figure out what bus number is assigned for CPUBUSNO(1) */
- reg32 = pci_mmio_read_config32(vtd_dev, VTD_CPUBUSNO);
- busno1 = (reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK;
+ uint32_t ubox_uart_en = 0, dfx1 = 0;
+ pci_devfn_t ubox_dev;
/* UBOX sits on CPUBUSNO(1) */
- ubox_dev = PCI_DEV(busno1, UBOX_DEV, UBOX_FUNC);
+ ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC);
uint32_t reset_sts = pci_mmio_read_config32(ubox_dev, UBOX_SC_RESET_STATUS);
/* In case we are in bypass mode do nothing */
if (reset_sts & UBOX_SC_BYPASS)
return;
- dfx1 = pci_mmio_read_config32(vtd_dev, VTD_DFX1);
+ dfx1 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_DFX1);
ubox_uart_en = pci_mmio_read_config32(ubox_dev, UBOX_UART_ENABLE);
switch (port) {
@@ -96,7 +90,7 @@ static void enable_integrated_uart(uint8_t port)
}
/* Disable decoding and enable the port we want */
- pci_mmio_write_config32(vtd_dev, VTD_DFX1, dfx1);
+ pci_mmio_write_config32(VTD_PCI_DEV, VTD_DFX1, dfx1);
pci_mmio_write_config32(ubox_dev, UBOX_UART_ENABLE, ubox_uart_en);
}