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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-08-17 11:49:27 +0530
committerAaron Durbin <adurbin@chromium.org>2017-08-25 18:06:25 +0000
commit4f6e341e88e94e81087a1538b3364dcd47641c7f (patch)
tree31f663abad816df9d4b7d9733d1773d34c78a35d /src/soc/intel
parent639bf8a4bd977ec6b44ee008cadcffca85ae61e2 (diff)
downloadcoreboot-4f6e341e88e94e81087a1538b3364dcd47641c7f.tar.xz
soc/intel/common: Add function to DLOCK PR registers
Add a function in FAST_SPI library to discrete lock the PR registers 0 to 4. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/fast_spi/fast_spi.c17
-rw-r--r--src/soc/intel/common/block/fast_spi/fast_spi_def.h8
-rw-r--r--src/soc/intel/common/block/include/intelblocks/fast_spi.h5
3 files changed, 30 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index f7ef68561f..078e0ae1f1 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -153,6 +153,23 @@ void fast_spi_lock_bar(void)
}
/*
+ * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the
+ * FAST_SPI Protected Range (PR) registers.
+ */
+void fast_spi_pr_dlock(void)
+{
+ void *spibar = fast_spi_get_bar();
+ uint32_t dlock;
+
+ dlock = read32(spibar + SPIBAR_DLOCK);
+ dlock |= (SPIBAR_DLOCK_PR0LOCKDN | SPIBAR_DLOCK_PR1LOCKDN
+ | SPIBAR_DLOCK_PR2LOCKDN | SPIBAR_DLOCK_PR3LOCKDN
+ | SPIBAR_DLOCK_PR4LOCKDN);
+
+ write32(spibar + SPIBAR_DLOCK, dlock);
+}
+
+/*
* Set FAST_SPIBAR Soft Reset Data Register value.
*/
void fast_spi_set_strap_msg_data(uint32_t soft_reset_data)
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
index 8e06df28de..a389e34154 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
@@ -34,6 +34,7 @@
#define SPIBAR_BFPREG 0x00
#define SPIBAR_HSFSTS_CTL 0x04
#define SPIBAR_FADDR 0x08
+#define SPIBAR_DLOCK 0x0c
#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4)
#define SPIBAR_FPR_BASE 0x84
#define SPIBAR_FPR(n) 0x84 + (4 * n))
@@ -87,6 +88,13 @@
/* Bit definitions for FADDR (0x08) register */
#define SPIBAR_FADDR_MASK 0x7FFFFFF
+/* Bit definitions for DLOCK (0x0C) register */
+#define SPIBAR_DLOCK_PR0LOCKDN (1 << 8)
+#define SPIBAR_DLOCK_PR1LOCKDN (1 << 9)
+#define SPIBAR_DLOCK_PR2LOCKDN (1 << 10)
+#define SPIBAR_DLOCK_PR3LOCKDN (1 << 11)
+#define SPIBAR_DLOCK_PR4LOCKDN (1 << 12)
+
/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
#define SPIBAR_FDATA_FIFO_SIZE 0x40
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
index b399e4d8fa..086143bc5f 100644
--- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h
+++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
@@ -49,6 +49,11 @@ void fast_spi_set_opcode_menu(void);
*/
void fast_spi_lock_bar(void);
/*
+ * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the
+ * FAST_SPI Protected Range (PR) registers.
+ */
+void fast_spi_pr_dlock(void);
+/*
* Set FAST_SPIBAR Soft Reset Data Register value.
*/
void fast_spi_set_strap_msg_data(uint32_t soft_reset_data);