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authorShelley Chen <shchen@chromium.org>2018-01-31 15:55:50 -0800
committerShelley Chen <shchen@google.com>2018-02-05 19:22:44 +0000
commit50db9a208e743ecbbadfde6643e7aeaf425eacdf (patch)
treed44550cee106f574f3e3198ec38546083c87d997 /src/soc/intel
parent1177bf516540b62e54cefdf346bb6e8a7c376642 (diff)
downloadcoreboot-50db9a208e743ecbbadfde6643e7aeaf425eacdf.tar.xz
soc/intel/skylake: Set PsysPl3 and Pl4
If given a value for PsysPl3 and/or Pl4, set the appropriate MSR. BUG=b:71594855 BRANCH=None TEST=boot up and check MSRs in OS to make sure values are set as expected. Test on Fizz, which will set these values in mainboard. Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/msr.h2
-rw-r--r--src/soc/intel/skylake/chip.h10
-rw-r--r--src/soc/intel/skylake/cpu.c32
-rw-r--r--src/soc/intel/skylake/include/soc/msr.h1
4 files changed, 45 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 45f201c7da..7aa81f09ea 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -114,6 +114,8 @@
#define PKG_POWER_LIMIT_CLAMP (1 << 16)
#define PKG_POWER_LIMIT_TIME_SHIFT 17
#define PKG_POWER_LIMIT_TIME_MASK (0x7f)
+#define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24
+#define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f)
/* SMM save state MSRs */
#define SMBASE_MSR 0xc20
#define IEDBASE_MSR 0xc22
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 4e8cb8155d..7c95ec1b0e 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -100,6 +100,16 @@ struct soc_intel_skylake_config {
/* SysPL2 Value in Watts */
u32 tdp_psyspl2;
+ /* SysPL3 Value in Watts */
+ u32 tdp_psyspl3;
+ /* SysPL3 window size */
+ u32 tdp_psyspl3_time;
+ /* SysPL3 duty cycle */
+ u32 tdp_psyspl3_dutycycle;
+
+ /* PL4 Value in Watts */
+ u32 tdp_pl4;
+
/*
* The following fields come from FspUpdVpd.h.
* These are configuration values that are passed to FSP during
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 291a40da3e..6e98afaffd 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -191,6 +191,38 @@ void set_power_limits(u8 power_limit_1_time)
wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
}
+ /* Set PsysPl3 */
+ if (conf->tdp_psyspl3) {
+ limit = rdmsr(MSR_PL3_CONTROL);
+ limit.lo = 0;
+ printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n",
+ conf->tdp_psyspl3);
+ limit.lo |= (conf->tdp_psyspl3 * power_unit) &
+ PKG_POWER_LIMIT_MASK;
+ /* Enable PsysPl3 */
+ limit.lo |= PKG_POWER_LIMIT_EN;
+ /* set PsysPl3 time window */
+ limit.lo |= (conf->tdp_psyspl3_time &
+ PKG_POWER_LIMIT_TIME_MASK) <<
+ PKG_POWER_LIMIT_TIME_SHIFT;
+ /* set PsysPl3 duty cycle */
+ limit.lo |= (conf->tdp_psyspl3_dutycycle &
+ PKG_POWER_LIMIT_DUTYCYCLE_MASK) <<
+ PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;
+ wrmsr(MSR_PL3_CONTROL, limit);
+ }
+
+ /* Set Pl4 */
+ if (conf->tdp_pl4) {
+ limit = rdmsr(MSR_VR_CURRENT_CONFIG);
+ limit.lo = 0;
+ printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n",
+ conf->tdp_pl4);
+ limit.lo |= (conf->tdp_pl4 * power_unit) &
+ PKG_POWER_LIMIT_MASK;
+ wrmsr(MSR_VR_CURRENT_CONFIG, limit);
+ }
+
/* Set DDR RAPL power limit by copying from MMIO to MSR */
msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index 0bd7f3ce60..780f94fdc9 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -36,6 +36,7 @@
#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
#define MSR_VR_CURRENT_CONFIG 0x601
#define MSR_VR_MISC_CONFIG 0x603
+#define MSR_PL3_CONTROL 0x615
#define MSR_VR_MISC_CONFIG2 0x636
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP1_POWER_LIMIT 0x640