diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-04-07 20:45:28 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-14 09:52:16 +0000 |
| commit | 59431176471beac2e074cf0ebca50c98c1ab50c8 (patch) | |
| tree | f350d86c863125d2d5ad862be42d68212c40ab08 /src/soc/intel | |
| parent | ba41ee1f0a74cf6b0ed0c068b6560e60f7d760eb (diff) | |
| download | coreboot-59431176471beac2e074cf0ebca50c98c1ab50c8.tar.xz | |
soc/intel/tigerlake: Configure RP setting
Add LTR and AER configuration to the root ports config.
BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 7 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e105061872..bc6c3db726 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -118,6 +118,12 @@ struct soc_intel_tigerlake_config { L1_SS_L1_2, } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + /* PCIe LTR: Enable (1) / Disable (0) */ + uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + + /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ + uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; + /* SMBus */ uint8_t SmbusEnable; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index ff6d3a978a..231399c676 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -122,10 +122,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* RP Configs */ - for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpL1Substates[i] = get_l1_substate_control(config->PcieRpL1Substates[i]); - + params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; + params->PcieRpAdvancedErrorReporting[i] = + config->PcieRpAdvancedErrorReporting[i]; + } /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); if (dev) { |