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| author | Krzysztof Sywula <krzysztof.m.sywula@intel.com> | 2019-03-21 17:11:02 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-27 08:33:21 +0000 |
| commit | 9bc9da9d7e32a73f7c051327a77ed6ab445a1e0b (patch) | |
| tree | 59095eb742cb428d5ca6347a41567fc23293306d /src/soc/intel | |
| parent | 7458629de369a220ea24afdfbf5f1dc9fdc36a5e (diff) | |
| download | coreboot-9bc9da9d7e32a73f7c051327a77ed6ab445a1e0b.tar.xz | |
soc/intel/cannonlake: Configure voltage margining policies
For systems that integrate GbE controllers, following parameters should be configured:
SlpS0WithGbeSupport: enable PchPmSlpS0VmRuntimeControl: disable,
PchPmSlpS0Vm070VSupport: disable, PchPmSlpS0Vm075VSupport: disable.
TEST=boot on any GbE supported WHL platform
Change-Id: I02aaf0b77b8fc1555a3a424c02acfada21707d0e
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 9 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 9 |
2 files changed, 17 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 5d9c744b31..a81a7c1211 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -138,6 +138,15 @@ struct soc_intel_cannonlake_config { uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; + /* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */ + uint8_t SlpS0WithGbeSupport; + /* SLP_S0 Voltage Margining Policy. 0: disable, 1: enable */ + uint8_t PchPmSlpS0VmRuntimeControl; + /* SLP_S0 Voltage Margining 0.70V Policy. 0: disable, 1: enable */ + uint8_t PchPmSlpS0Vm070VSupport; + /* SLP_S0 Voltage Margining 0.75V Policy. 0: disable, 1: enable */ + uint8_t PchPmSlpS0Vm075VSupport; + /* Audio related */ uint8_t PchHdaDspEnable; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 1a3b4fbea2..6173403395 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -161,8 +161,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) dev = dev_find_slot(0, PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; - else + else { params->PchLanEnable = dev->enabled; + if (config->s0ix_enable) { + params->SlpS0WithGbeSupport = 1; + params->PchPmSlpS0VmRuntimeControl = 0; + params->PchPmSlpS0Vm070VSupport = 0; + params->PchPmSlpS0Vm075VSupport = 0; + } + } /* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; |