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authorSubrata Banik <subrata.banik@intel.com>2019-05-14 17:31:19 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-05-20 14:49:54 +0000
commitabdc9bc8c8605f2865b7a9cc956cbcc4402c1c43 (patch)
tree15c229ca6e60130c1e408f1cc18339ac0e941963 /src/soc/intel
parent8ef6732b94148a39f8203cb3b4cf3388dc103199 (diff)
downloadcoreboot-abdc9bc8c8605f2865b7a9cc956cbcc4402c1c43.tar.xz
soc/intel/common/block/gpio: Add gpio_pm_configure() function
This patch adds new function to perform gpio power management programming as per EDS. BUG=b:130764684 TEST=Able to build and boot from fixed media on ICL and CML. Change-Id: I816a70ad92595f013740a235a9799912ad51665e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/gpio/gpio.c18
-rw-r--r--src/soc/intel/common/block/include/intelblocks/gpio.h20
2 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index 3a0594cba1..d37601ce3b 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -609,3 +609,21 @@ void gpi_clear_int_cfg(void)
}
}
}
+
+/* The function performs GPIO Power Management programming. */
+void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num)
+{
+ int i;
+ size_t gpio_communities;
+ uint8_t misccfg_pm_mask = MISCCFG_ENABLE_GPIO_PM_CONFIG;
+ const struct pad_community *comm;
+
+ comm = soc_gpio_get_community(&gpio_communities);
+ if (gpio_communities != num)
+ die("Incorrect GPIO community count!\n");
+
+ /* Program GPIO_MISCCFG */
+ for (i = 0; i < num; i++, comm++)
+ pcr_rmw8(comm->port, GPIO_MISCCFG,
+ misccfg_pm_mask, misccfg_pm_values[i]);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index 417929329f..a2cccc7cd2 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -23,6 +23,23 @@
#ifndef __ACPI__
#include <types.h>
+/* GPIO community IOSF sideband clock gating */
+#define MISCCFG_GPSIDEDPCGEN (1 << 5)
+/* GPIO community RCOMP clock gating */
+#define MISCCFG_GPRCOMPCDLCGEN (1 << 4)
+/* GPIO community RTC clock gating */
+#define MISCCFG_GPRTCDLCGEN (1 << 3)
+/* GFX controller clock gating */
+#define MISCCFG_GSXSLCGEN (1 << 2)
+/* GPIO community partition clock gating */
+#define MISCCFG_GPDPCGEN (1 << 1)
+/* GPIO community local clock gating */
+#define MISCCFG_GPDLCGEN (1 << 0)
+/* Enable GPIO community power management configuration */
+#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
/*
* GPIO numbers may not be contiguous and instead will have a different
* starting pin number for each pad group.
@@ -215,5 +232,8 @@ uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg,
*/
void gpi_clear_int_cfg(void);
+/* The function performs GPIO Power Management programming. */
+void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num);
+
#endif
#endif /* _SOC_INTELBLOCKS_GPIO_H_ */