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authorSubrata Banik <subrata.banik@intel.com>2020-10-28 13:25:06 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-10-29 10:49:03 +0000
commitb544fe48af76e5aae7537d95b62191e1fed2bc45 (patch)
tree1a4ec089b065138d084dcedbf0d4f0f3e4eed752 /src/soc/intel
parent68e597d81e41bb2d93558e4a4da26f0892f34d86 (diff)
downloadcoreboot-b544fe48af76e5aae7537d95b62191e1fed2bc45.tar.xz
mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'
List of changes: 1. Split mem_cfg for DDR4 and LPDDR4 as per board_id 2. Move dq_pins_interleaved into board-specific memory configuration information TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs. Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/alderlake/include/soc/meminit.h6
-rw-r--r--src/soc/intel/alderlake/meminit.c1
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h
index 76930be0e7..5fed5680c6 100644
--- a/src/soc/intel/alderlake/include/soc/meminit.h
+++ b/src/soc/intel/alderlake/include/soc/meminit.h
@@ -77,6 +77,12 @@ struct mb_cfg {
uint16_t rcomp_targets[5];
/*
+ * Dqs Pins Interleaved Setting. Enable/Disable Control
+ * TRUE = enable, FALSE = disable
+ */
+ bool dq_pins_interleaved;
+
+ /*
* Early Command Training Enable/Disable Control
* TRUE = enable, FALSE = disable
*/
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index e7084a5a16..f5f747d79b 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -180,4 +180,5 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg,
mem_cfg->ECT = board_cfg->ect;
mem_cfg->UserBd = board_cfg->UserBd;
+ mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved;
}