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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-18 06:01:41 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-20 15:28:13 +0000
commitb7908d2b08988e19970f27ec4272dd3bb6c4eca2 (patch)
tree15a7d8ed7070fa7db44a498646c19b85809542ab /src/soc/intel
parent9172b6920cac2c4dabf19e529dbfed91b15685c5 (diff)
downloadcoreboot-b7908d2b08988e19970f27ec4272dd3bb6c4eca2.tar.xz
intel/apollolake: Move LPC decode enables to bootblock
Doing this allows to call console_init() earlier in romstage. This also fixes IO UART in bootblock, although it appears there is currently no board that was affected. Change-Id: Iec363a8c651cc1b05b24229db09d686938118f3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34969 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/bootblock/bootblock.c3
-rw-r--r--src/soc/intel/apollolake/romstage.c7
2 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 7b4eaef430..f86c18ed43 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -21,6 +21,7 @@
#include <device/pci_ops.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/lpc_lib.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
@@ -96,6 +97,8 @@ void bootblock_soc_early_init(void)
/* Prepare UART for serial console. */
if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
uart_bootblock_init();
+ if (CONFIG(DRIVERS_UART_8250IO))
+ lpc_io_setup_comm_a_b();
if (CONFIG(TPM_ON_FAST_SPI))
tpm_enable();
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 640208dd0f..fb8473c512 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -91,9 +91,6 @@ static void soc_early_romstage_init(void)
/* Enable decoding for HPET. Needed for FSP global pointer storage */
pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
P2SB_HPTC_ADDRESS_ENABLE);
-
- if (CONFIG(DRIVERS_UART_8250IO))
- lpc_io_setup_comm_a_b();
}
/* Thermal throttle activation offset */
@@ -207,10 +204,10 @@ asmlinkage void car_stage_entry(void)
timestamp_add_now(TS_START_ROMSTAGE);
- soc_early_romstage_init();
-
console_init();
+ soc_early_romstage_init();
+
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);