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authorDuncan Laurie <dlaurie@chromium.org>2017-03-07 19:03:50 -0800
committerDuncan Laurie <dlaurie@chromium.org>2017-03-08 19:07:49 +0100
commitcb76d50f0d15eada406e51a096d78553e3d4184e (patch)
treea3ed5bb7cd23fd99fa4cdc385b8366e66f3b0990 /src/soc/intel
parentb2aac8503019aad122983c0b60635357e9087b9c (diff)
downloadcoreboot-cb76d50f0d15eada406e51a096d78553e3d4184e.tar.xz
intel/skylake: Add function to read state of Deep S5
Add a function to read the current state of Deep S5 configuration and indicate if it is enabled (for AC and/or DC) or disabled. This is similar to the existing function that checks Deep S3 enable state. BUG=b:36042662 BRANCH=none TEST=tested with subsequent commits to check Deep S5 state at boot and filter event log messages if it is enabled. Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/include/soc/pm.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 0045fa04e8..7112c77a24 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -198,4 +198,12 @@ static inline int deep_s3_enabled(void)
return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
}
+static inline int deep_s5_enabled(void)
+{
+ uint32_t deep_s5_pol;
+
+ deep_s5_pol = read32(pmc_mmio_regs() + S5_PWRGATE_POL);
+ return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS));
+}
+
#endif