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| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2020-07-03 14:14:49 +0800 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2020-07-07 04:18:55 +0000 |
| commit | d964fea5a64d82d7f63ea7b39d6b4ea5e944d15c (patch) | |
| tree | 21f87d5e45f417539c0babe543c5cfb5cb0fd5df /src/soc/intel | |
| parent | cdd84e7f62bde746c6bea94b0430caf9602eb327 (diff) | |
| download | coreboot-d964fea5a64d82d7f63ea7b39d6b4ea5e944d15c.tar.xz | |
lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL:
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E
BUG=b:159195585,b:152936481,b:156435028
TEST=build.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt index 49fe4454e4..f57b372bac 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt @@ -11,3 +11,5 @@ K4U6E3S4AA-MGCR,spd-1.hex MT53E512M32D2NP-046 WT:E,spd-1.hex H9HCNNNCPMMLXR-NEE,spd-3.hex K4UBE3D4AA-MGCR,spd-3.hex +MT53E512M64D4NW-046 WT:E,spd-1.hex +MT53E1G64D8NW-046 WT:E,spd-3.hex |