summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorMichael Niewöhner <foss@mniewoehner.de>2020-03-31 00:28:57 +0200
committerMatt DeVillier <matt.devillier@gmail.com>2020-04-03 16:23:01 +0000
commite4c784bd0d91fe0bf4e0e8e5b0c9fa173235cea6 (patch)
treeda7124d9201f897bb7c1afc632cf8b6cf1e9680f /src/soc/intel
parentae01122b57eed272d6a10013b4686826dbfb95be (diff)
downloadcoreboot-e4c784bd0d91fe0bf4e0e8e5b0c9fa173235cea6.tar.xz
soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
There are boards that do not need a specific domain_vr_config because the defaults provided by the soc code are sufficient. Currently, this means that these boards can't benefit from lower power states (PSI 3 and 4) because the settings default to being disabled since at the time the defaults have been defined (2015) there were bugs in FSP in this regard. Set the default values of psiXenable to 1 for boards that do not have a domain_vr_config setting in their devicetree, just like Cannon Lake does. Boards that have a domain_vr_config and set their specific settings are not affected at all. Currently, there are only three boards that have no domain_vr_config: - supermicro/x11-lga1151-series These boards have a MPS MP2955 which we can assume support for PS3 (the MP2965 and MP2935 support it, too). S-series CPUs with a 1151 socket do not have C9/C10 but only C8 and since only C10 makes use of PS4, those CPUs won't ever request PS4. That means we do not need to disable it explicitly for these boards. - 51nb/x210: Needs testing and/or VR datasheet check for PS3/PS4 support Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39980 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/vr_config.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 98d2513ec5..57c55eca76 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -21,15 +21,15 @@
#include <console/console.h>
#include <intelblocks/cpulib.h>
-/* Default values for domain configuration. PSI3 and PSI4 are disabled. */
+/* Default values for domain configuration. */
static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
[VR_SYSTEM_AGENT] = {
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(4),
.psi3threshold = VR_CFG_AMP(1),
- .psi3enable = 0,
- .psi4enable = 0,
+ .psi3enable = 1,
+ .psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
@@ -40,8 +40,8 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
- .psi3enable = 0,
- .psi4enable = 0,
+ .psi3enable = 1,
+ .psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
@@ -52,8 +52,8 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
- .psi3enable = 0,
- .psi4enable = 0,
+ .psi3enable = 1,
+ .psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,
@@ -64,8 +64,8 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
- .psi3enable = 0,
- .psi4enable = 0,
+ .psi3enable = 1,
+ .psi4enable = 1,
.imon_slope = 0,
.imon_offset = 0,
.icc_max = 0,