diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2020-11-19 15:13:02 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:17:53 +0000 |
| commit | 0948b363b0568e70af2352566dee39e0df82d96d (patch) | |
| tree | 9650cab7fd8c363716cce9c93cb6cf058f7a1644 /src/soc/intel | |
| parent | c022a795033062ed1b1908d18fa419444e42aceb (diff) | |
| download | coreboot-0948b363b0568e70af2352566dee39e0df82d96d.tar.xz | |
soc/intel/braswell/bootblock/bootblock.c: Report the FSP-T output
Report the FSP temporary RAM location
Tested on Facebook FBG1701
Change-Id: Ia2ce48f7a7948d1fe51ad1ca33b8fb385674cb41
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/braswell/bootblock/bootblock.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 10ac02584d..ae1c97a9c4 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -5,6 +5,7 @@ #include <build.h> #include <console/console.h> #include <device/pci_ops.h> +#include <fsp/util.h> #include <pc80/mc146818rtc.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -117,6 +118,8 @@ void bootblock_soc_early_init(void) } void bootblock_soc_init(void) { + report_fsp_output(); + /* Continue chipset initialization */ soc_rtc_init(); set_max_freq(); |