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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-13 16:07:12 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-15 08:34:29 +0000 |
| commit | 0c0bcd4072746582d8837dd7eca2f1731ce35561 (patch) | |
| tree | ceffd06a146e1b6e1688cfc6d6e7d7bef96b4130 /src/soc/intel | |
| parent | 7c1fe4bd122602272a3f2c7d7c2fbc3124cf2f8d (diff) | |
| download | coreboot-0c0bcd4072746582d8837dd7eca2f1731ce35561.tar.xz | |
PCI IDs: Add PCI ID for JSL DPTF/DTT PCI device
This PCI ID is required in order for JSL devices to perform SSDT
generation for DPTF.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/dtt/dtt.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c index 14987ead0a..f3969939c9 100644 --- a/src/soc/intel/common/block/dtt/dtt.c +++ b/src/soc/intel/common/block/dtt/dtt.c @@ -6,6 +6,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_TGL_DTT, + PCI_DEVICE_ID_INTEL_JSL_DTT, }; static struct device_operations dptf_dev_ops = { |