diff options
| author | Caveh Jalali <caveh@google.com> | 2018-03-08 17:58:21 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-14 11:19:08 +0000 |
| commit | 21df67ecd467c82f87ac80a658522c3fbf70a144 (patch) | |
| tree | c08195b9479903490f593fd5fde4a9132d292a49 /src/soc/intel | |
| parent | 995d989ecbc7d17cf35ead1e5948b94eb22e1036 (diff) | |
| download | coreboot-21df67ecd467c82f87ac80a658522c3fbf70a144.tar.xz | |
soc/intel/cannonlake: Disable RTC write protect
The cannonlake FSP enables PchLockDownRtcMemoryLock by default, but we
need this memory to be writable. We normally over-ride this in the
SoC chip init code, so we'll do the same on cannonlake.
BUG=b:71722386
BRANCH=none
TEST=Filled /dev/nvram with 0xff and 0x00 bytes to verify we can flip
all the bits.
Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/25069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 2187f906cf..ca2f9a35ec 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -200,6 +200,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); + /* Unlock upper 8 bytes of RTC RAM */ + params->PchLockDownRtcMemoryLock = 0; + /* SATA */ params->SataEnable = config->SataEnable; params->SataMode = config->SataMode; |