diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-06-28 17:37:09 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-02 03:27:12 +0200 |
| commit | 24a594f42a16b523534667ced65b06eb32bef1a0 (patch) | |
| tree | 1421e552df7b8642ccb4162279430e8692cf03d8 /src/soc/intel | |
| parent | ccae9aec5384100c0761eabf38f6e85c3bf02c3e (diff) | |
| download | coreboot-24a594f42a16b523534667ced65b06eb32bef1a0.tar.xz | |
soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not needed
On Apollolake CSE can be used to fetch firmware from boot media. However,
when this feature is not used, CSE needs to be explicitly notified of it
before memory training is complete. This way it can transition to next
state.
BUG=chrome-os-partner:53876
TEST=CSE can be power-gated during S0iX. Confirmed with LTB.
Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15494
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ce28326392..049bf4fe61 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -241,6 +241,14 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) } else printk(BIOS_DEBUG, "MRC cache was not found\n"); } + + /* + * Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch + * firmware for us if we are using memory-mapped SPI. This lets CSE + * state machine transition to next boot state, so that it can function + * as designed. + */ + mupd->FspmConfig.SkipCseRbp = IS_ENABLED(CONFIG_SPI_FLASH_MEMORY_MAPPED); } __attribute__ ((weak)) |