diff options
| author | John Zhao <john.zhao@intel.com> | 2021-04-17 13:45:00 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-26 08:27:46 +0000 |
| commit | 24ae31cdc6940320bd0a5cccf2d991b2fd31e236 (patch) | |
| tree | 3b3cb3401e602037af143e4ac3f97750fe241dfe /src/soc/intel | |
| parent | ae3f524a1f7dfe52331ef4cbaf8fc317f260fe7a (diff) | |
| download | coreboot-24ae31cdc6940320bd0a5cccf2d991b2fd31e236.tar.xz | |
soc/intel/alderlake: Fix devices list in the DMAR DRHD structure
The VT-d specification states that device scope for remapping hardware
unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list
of hardware unit definition structure. This change fixes the devices
list in the DMAR DRHD structure.
BUG=None
TEST=Built image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I14c34ad66a5ee8c30acabd8fe5a05c22087f9120
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/acpi.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index db005e8bcf..664c40ba3d 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -198,6 +198,23 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } + /* TCSS Thunderbolt root ports */ + for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { + const struct device *const tbt_dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); + if (is_dev_enabled(tbt_dev)) { + const uint64_t tbtbar = MCHBAR64(TBTxBAR(i)) & VTBAR_MASK; + const bool tbten = MCHBAR32(TBTxBAR(i)) & VTBAR_ENABLED; + if (tbtbar && tbten) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_ds_pci_br(current, 0, 7, i); + + acpi_dmar_drhd_fixup(tmp, current); + } + } + } + const uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; const bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; @@ -216,23 +233,6 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } - /* TCSS Thunderbolt root ports */ - for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { - const struct device *const tbt_dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); - if (is_dev_enabled(tbt_dev)) { - const uint64_t tbtbar = MCHBAR64(TBTxBAR(i)) & VTBAR_MASK; - const bool tbten = MCHBAR32(TBTxBAR(i)) & VTBAR_ENABLED; - if (tbtbar && tbten) { - const unsigned long tmp = current; - - current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); - current += acpi_create_dmar_ds_pci_br(current, 0, 7, i); - - acpi_dmar_drhd_fixup(tmp, current); - } - } - } - /* Add RMRR entry */ if (is_dev_enabled(igfx_dev)) { const unsigned long tmp = current; |