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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-25 23:43:14 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-26 11:47:27 +0000 |
| commit | 47a6603f34481e1226c106002c9fd7fb3d0c2c04 (patch) | |
| tree | b6a8be37ffb19e95eee8e15983052c2b9faa18e3 /src/soc/intel | |
| parent | a3eb1252383a51775f6c470b5a44d83bd6c913c5 (diff) | |
| download | coreboot-47a6603f34481e1226c106002c9fd7fb3d0c2c04.tar.xz | |
sb/intel/common/spi: Add Baytrail/Braswell support
The mechanism for getting the SPIBAR is little different.
Tested on Intel Minnowboard Turbot.
Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/broadwell/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 07bcf22b1d..21c9b6f12a 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,7 +20,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT |