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| author | Furquan Shaikh <furquan@google.com> | 2020-06-01 13:47:28 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-03 12:22:25 +0000 |
| commit | 4b4c0c6016fb1be88b770077c00e788421bef2fe (patch) | |
| tree | 5fca5d8c10b086ca462cc148e2ab2dd4fc50415b /src/soc/intel | |
| parent | 9e94cce35d9e0a22ac169c5e5d4cb7100af730d1 (diff) | |
| download | coreboot-4b4c0c6016fb1be88b770077c00e788421bef2fe.tar.xz | |
northbridge/intel/sandybridge: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: Ib0ffd9a332fa9590de63f8828d30daa710fe50db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions