soc/intel/denverton_ns: Update UART legacy mode to keep FSP traces

The FSP can only output its traces when the HSUART PCI device is
available.

- Move the hiding to after last FSP call.
- Adapt coreboot PCI enumeration to keep the legacy configuration.

With UART configured as legacy Linux will not re-enumerate it but detects
it as legacy (ttyS0 instead of ttyS4).

Change-Id: Id8801e178ffd8eeee78ece07da7bd6b8dbd88538
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>

2 files changed, 39 insertions, 9 deletions

diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c
index affddbaec2..9af42ee217 100644
--- a/src/soc/intel/denverton_ns/bootblock/uart.c
+++ b/src/soc/intel/denverton_ns/bootblock/uart.c
@@ -65,15 +65,6 @@ static void pci_early_hsuart_device_probe(u8 bus, u8 dev, u8 func,
 			     SIZE_OF_HSUART_RES * func + PSR_OFFSET);
 	*psr_reg >>= 1;
 #endif
-
-#if (IS_ENABLED(CONFIG_LEGACY_UART_MODE))
-	/* Hide HSUART on PCI to prevent re-enumeration
-	 * and enable legacy mode.
-	 */
-	pci_write_config32(uart_dev, PCI_FUNC_RDCFG_HIDE,
-			   pci_read_config32(uart_dev, PCI_FUNC_RDCFG_HIDE) |
-			       1);
-#endif
 }
 
 static void early_config_gpio(void)
diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c
index ca4e8b5979..78f1d56fd0 100644
--- a/src/soc/intel/denverton_ns/uart.c
+++ b/src/soc/intel/denverton_ns/uart.c
@@ -26,11 +26,26 @@
 #include <device/pci_ids.h>
 #include <soc/pci_devs.h>
 #include <console/console.h>
+#include <soc/uart.h>
+#include <fsp/api.h>
 
 static void dnv_ns_uart_read_resources(struct device *dev)
 {
 	/* read resources to be visible in the log*/
 	pci_dev_read_resources(dev);
+	if (!IS_ENABLED(CONFIG_LEGACY_UART_MODE))
+		return;
+	struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (res == NULL)
+		return;
+	res->size = 0x8;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	/* Do not configure membar */
+	res = find_resource(dev, PCI_BASE_ADDRESS_1);
+	if (res != NULL)
+		res->flags = 0;
+	compact_resources(dev);
+
 }
 
 static struct device_operations uart_ops = {
@@ -51,3 +66,27 @@ static const struct pci_driver uart_driver __pci_driver = {
 	.vendor = PCI_VENDOR_ID_INTEL,
 	.devices = uart_ids
 };
+
+static void hide_hsuarts(void)
+{
+	int i;
+	printk(BIOS_DEBUG, "HIDING HSUARTs.\n");
+	/* There is a hardware requirement to hide functions starting from the
+	   last one. */
+	for (i = DENVERTON_UARTS_TO_INI - 1; i >= 0; i--) {
+		struct device *uart_dev;
+		uart_dev = dev_find_slot(0, PCI_DEVFN(HSUART_DEV, i));
+		if (uart_dev == NULL)
+			continue;
+		pci_or_config32(uart_dev, PCI_FUNC_RDCFG_HIDE, 1);
+	}
+}
+
+/* Hide HSUART PCI device very last when FSP no longer needs it */
+void platform_fsp_notify_status(enum fsp_notify_phase phase)
+{
+	if (phase != END_OF_FIRMWARE)
+		return;
+	if (IS_ENABLED(CONFIG_LEGACY_UART_MODE))
+		hide_hsuarts();
+}