diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-09-29 19:37:49 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-10-07 17:55:29 +0200 |
| commit | 5d0847f7571b4b76a38b9ef5276ec0967f664833 (patch) | |
| tree | fc74b8ac446f0afa9c2e85ebedcd7833e1201611 /src/soc/intel | |
| parent | 509c4c409c1ee272206f3369e42cd1ba4e1cc8d0 (diff) | |
| download | coreboot-5d0847f7571b4b76a38b9ef5276ec0967f664833.tar.xz | |
Revert "soc/intel/apollolake: Add pmc_ipc device support"
This reverts commit 28821dbb2261267462a7e9b0cc1c23b51af2d3ee.
(https://review.coreboot.org/16649)
This change causes the kernel to boot really slow. Maybe there is an
interrupt storm that prevents the kernel from making any
progress. Reverting until the proper kernel dependency is met.
BUG=chrome-os-partner:57364
BRANCH=None
TEST=Kernels boots to prompt fine on DVT.
Change-Id: I1c9913b4476a08303f9dd887b8631601c847dcf7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7014ee1bb88df7a2d7f6b3dced797fef75b252d
Original-Change-Id: I061c0b03b43b516a190b370c04888e73a410fcf1
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/391233
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/16881
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/pmc_ipc.asl | 57 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/southbridge.asl | 3 |
2 files changed, 0 insertions, 60 deletions
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl deleted file mode 100644 index b89bebf5da..0000000000 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/iomap.h> - -#define MAILBOX_DATA 0x7080 -#define MAILBOX_INTF 0x7084 -#define PMIO_LENGTH 0x80 - -Device (IPC1) -{ - Name (_HID, "INT34D2") - Name (_CID, "INT34D2") - Name (_DDN, "Intel(R) IPC1 Controller") - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR) - Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT) - Memory32Fixed (ReadWrite, 0x0, 0x4, MINF) - IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE + PMIO_LENGTH, - 0x04, PMIO_LENGTH) - Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) - { - PMC_INT - } - }) - - Method (_CRS, 0x0, NotSerialized) - { - CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) - Store (PMC_BAR0, IBAS) - - CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) - Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA) - CreateDwordField (^RBUF, ^MINF._BAS, MIBA) - Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA) - - CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) - Store (PMC_SRAM_BASE_0, SBAS) - - Return (^RBUF) - } -} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f2b09c74eb..1c10f1a5ed 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -40,9 +40,6 @@ Scope (\_SB) #include "xhci.asl" -/* PMC IPC */ -#include "pmc_ipc.asl" - /* LPC */ #include "lpc.asl" |