soc/intel/cannonlake: Move the FSP related callbacks to separate files

Move funtions callbacks used to override FSP upd values to
separate files. This serves as a base change for SoCs for which
FSP is still under development, and hence the FSP header files
are not available yet and in turn the UPDs cannot be referred.
These newer SoCs will implement empty callbacks. The code will
compile with basic header files which only include the architectural
FSP structures.

This allows plugging in these separate files for compilation in an
environment where FSP header files are available.
The fact is, FSP header files are not released externally until PRQ.
However the teams at intel and some partners have access to the development
version of these files. This code refactor helps to continue development
on the pre-PRQ silicons and submit related code to coreboot.org.

BUG=None
BRANCH=None
TEST=Build for cnlrvp

Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

6 files changed, 299 insertions, 248 deletions

diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 065d92b6e5..0e4c805dca 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -37,6 +37,7 @@ ramstage-y += acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += finalize.c
+ramstage-y += fsp_params.c
 ramstage-y += gpio.c
 ramstage-y += graphics.c
 ramstage-y += gspi.c
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 34a2fe00c5..014805f593 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -95,43 +95,6 @@ const char *soc_acpi_name(const struct device *dev)
 }
 #endif
 
-static void parse_devicetree(FSP_S_CONFIG *params)
-{
-	struct device *dev = SA_DEV_ROOT;
-	if (!dev) {
-		printk(BIOS_ERR, "Could not find root device\n");
-		return;
-	}
-
-	const config_t *config = dev->chip_info;
-	const int SerialIoDev[] = {
-		PCH_DEVFN_I2C0,
-		PCH_DEVFN_I2C1,
-		PCH_DEVFN_I2C2,
-		PCH_DEVFN_I2C3,
-		PCH_DEVFN_I2C4,
-		PCH_DEVFN_I2C5,
-		PCH_DEVFN_GSPI0,
-		PCH_DEVFN_GSPI1,
-		PCH_DEVFN_GSPI2,
-		PCH_DEVFN_UART0,
-		PCH_DEVFN_UART1,
-		PCH_DEVFN_UART2
-	};
-
-	for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) {
-		dev = dev_find_slot(0, SerialIoDev[i]);
-		if (!dev->enabled) {
-			params->SerialIoDevMode[i] = PchSerialIoDisabled;
-			continue;
-		}
-		params->SerialIoDevMode[i] = PchSerialIoPci;
-		if (config->SerialIoDevMode[i] == PchSerialIoAcpi ||
-		    config->SerialIoDevMode[i] == PchSerialIoHidden)
-			params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
-	}
-}
-
 void soc_init_pre_device(void *chip_info)
 {
 	/* Perform silicon specific init. */
@@ -177,159 +140,3 @@ struct chip_operations soc_intel_cannonlake_ops = {
 	.enable_dev	= &soc_enable,
 	.init		= &soc_init_pre_device,
 };
-
-/* UPD parameters to be initialized before SiliconInit */
-void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
-{
-	int i;
-	FSP_S_CONFIG *params = &supd->FspsConfig;
-	FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
-	struct device *dev = SA_DEV_ROOT;
-	config_t *config = dev->chip_info;
-
-	/* Parse device tree and enable/disable devices */
-	parse_devicetree(params);
-
-	/* Load VBT before devicetree-specific config. */
-	params->GraphicsConfigPtr = (uintptr_t)vbt_get();
-
-	/* Set USB OC pin to 0 first */
-	for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
-		params->Usb2OverCurrentPin[i] = 0;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
-		params->Usb3OverCurrentPin[i] = 0;
-	}
-
-	mainboard_silicon_init_params(params);
-
-	/* Unlock upper 8 bytes of RTC RAM */
-	params->PchLockDownRtcMemoryLock = 0;
-
-	/* SATA */
-	dev = dev_find_slot(0, PCH_DEVFN_SATA);
-	if (!dev)
-		params->SataEnable = 0;
-	else {
-		params->SataEnable = dev->enabled;
-		params->SataMode = config->SataMode;
-		params->SataSalpSupport = config->SataSalpSupport;
-		memcpy(params->SataPortsEnable, config->SataPortsEnable,
-			sizeof(params->SataPortsEnable));
-		memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
-			sizeof(params->SataPortsDevSlp));
-	}
-
-	/* Lan */
-	dev = dev_find_slot(0, PCH_DEVFN_GBE);
-	if (!dev)
-		params->PchLanEnable = 0;
-	else
-		params->PchLanEnable = dev->enabled;
-
-	/* Audio */
-	params->PchHdaDspEnable = config->PchHdaDspEnable;
-	params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
-	params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
-	params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
-	params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
-	params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
-	params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
-	params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
-	params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
-	params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
-	params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
-
-	/* S0ix */
-	params->PchPmSlpS0Enable = config->s0ix_enable;
-
-	/* USB */
-	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
-		params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
-		params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
-		params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
-		params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
-		params->Usb2AfePredeemp[i] =
-			config->usb2_ports[i].tx_emp_enable;
-		params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
-		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
-		params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
-		if (config->usb3_ports[i].tx_de_emp) {
-			params->Usb3HsioTxDeEmphEnable[i] = 1;
-			params->Usb3HsioTxDeEmph[i] =
-				config->usb3_ports[i].tx_de_emp;
-		}
-		if (config->usb3_ports[i].tx_downscale_amp) {
-			params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
-			params->Usb3HsioTxDownscaleAmp[i] =
-				config->usb3_ports[i].tx_downscale_amp;
-		}
-	}
-
-	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
-	if (!xdci_can_enable())
-		dev->enabled = 0;
-	params->XdciEnable = dev->enabled;
-
-	/* PCI Express */
-	for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
-		if (config->PcieClkSrcUsage[i] == 0)
-			config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
-	}
-	memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
-	       sizeof(config->PcieClkSrcUsage));
-	memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
-	       sizeof(config->PcieClkSrcClkReq));
-
-	/* eMMC and SD */
-	dev = dev_find_slot(0, PCH_DEVFN_EMMC);
-	if (!dev)
-		params->ScsEmmcEnabled = 0;
-	else {
-		params->ScsEmmcEnabled = dev->enabled;
-		params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
-		params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
-		if (config->EmmcHs400DllNeed == 1) {
-			params->PchScsEmmcHs400RxStrobeDll1 =
-				config->EmmcHs400RxStrobeDll1;
-			params->PchScsEmmcHs400TxDataDll =
-				config->EmmcHs400TxDataDll;
-		}
-	}
-
-	dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
-	if (!dev)
-		params->ScsSdCardEnabled = 0;
-	else
-		params->ScsSdCardEnabled = dev->enabled;
-
-	dev = dev_find_slot(0, PCH_DEVFN_UFS);
-	if (!dev)
-		params->ScsUfsEnabled = 0;
-	else
-		params->ScsUfsEnabled = dev->enabled;
-
-	params->Heci3Enabled = config->Heci3Enabled;
-	params->Device4Enable = config->Device4Enable;
-	params->SkipMpInit = !chip_get_fsp_mp_init();
-
-	/* VrConfig Settings for 5 domains
-	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
-	 * 3 = GT unsliced,  4 = GT sliced */
-	for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
-		fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
-
-	/* Vt-D config */
-	tconfig->VtdDisable = config->VtdDisable;
-}
-
-/* Mainboard GPIO Configuration */
-__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
new file mode 100644
index 0000000000..cbc97b22cd
--- /dev/null
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -0,0 +1,220 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <chip.h>
+#include <compiler.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <intelblocks/xdci.h>
+#include <soc/intel/common/vbt.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <string.h>
+
+static void parse_devicetree(FSP_S_CONFIG *params)
+{
+	struct device *dev = SA_DEV_ROOT;
+	if (!dev) {
+		printk(BIOS_ERR, "Could not find root device\n");
+		return;
+	}
+
+	const config_t *config = dev->chip_info;
+	const int SerialIoDev[] = {
+		PCH_DEVFN_I2C0,
+		PCH_DEVFN_I2C1,
+		PCH_DEVFN_I2C2,
+		PCH_DEVFN_I2C3,
+		PCH_DEVFN_I2C4,
+		PCH_DEVFN_I2C5,
+		PCH_DEVFN_GSPI0,
+		PCH_DEVFN_GSPI1,
+		PCH_DEVFN_GSPI2,
+		PCH_DEVFN_UART0,
+		PCH_DEVFN_UART1,
+		PCH_DEVFN_UART2
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) {
+		dev = dev_find_slot(0, SerialIoDev[i]);
+		if (!dev->enabled) {
+			params->SerialIoDevMode[i] = PchSerialIoDisabled;
+			continue;
+		}
+		params->SerialIoDevMode[i] = PchSerialIoPci;
+		if (config->SerialIoDevMode[i] == PchSerialIoAcpi ||
+		    config->SerialIoDevMode[i] == PchSerialIoHidden)
+			params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
+	}
+}
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+	int i;
+	FSP_S_CONFIG *params = &supd->FspsConfig;
+	FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
+	struct device *dev = SA_DEV_ROOT;
+	config_t *config = dev->chip_info;
+
+	/* Parse device tree and enable/disable devices */
+	parse_devicetree(params);
+
+	/* Load VBT before devicetree-specific config. */
+	params->GraphicsConfigPtr = (uintptr_t)vbt_get();
+
+	/* Set USB OC pin to 0 first */
+	for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
+		params->Usb2OverCurrentPin[i] = 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
+		params->Usb3OverCurrentPin[i] = 0;
+	}
+
+	mainboard_silicon_init_params(params);
+
+	/* Unlock upper 8 bytes of RTC RAM */
+	params->PchLockDownRtcMemoryLock = 0;
+
+	/* SATA */
+	dev = dev_find_slot(0, PCH_DEVFN_SATA);
+	if (!dev)
+		params->SataEnable = 0;
+	else {
+		params->SataEnable = dev->enabled;
+		params->SataMode = config->SataMode;
+		params->SataSalpSupport = config->SataSalpSupport;
+		memcpy(params->SataPortsEnable, config->SataPortsEnable,
+			sizeof(params->SataPortsEnable));
+		memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
+			sizeof(params->SataPortsDevSlp));
+	}
+
+	/* Lan */
+	dev = dev_find_slot(0, PCH_DEVFN_GBE);
+	if (!dev)
+		params->PchLanEnable = 0;
+	else
+		params->PchLanEnable = dev->enabled;
+
+	/* Audio */
+	params->PchHdaDspEnable = config->PchHdaDspEnable;
+	params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
+	params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
+	params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
+	params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
+	params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
+	params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
+	params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
+	params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
+	params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
+	params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
+
+	/* S0ix */
+	params->PchPmSlpS0Enable = config->s0ix_enable;
+
+	/* USB */
+	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
+		params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
+		params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+		params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
+		params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
+		params->Usb2AfePredeemp[i] =
+			config->usb2_ports[i].tx_emp_enable;
+		params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
+		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+		params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+		if (config->usb3_ports[i].tx_de_emp) {
+			params->Usb3HsioTxDeEmphEnable[i] = 1;
+			params->Usb3HsioTxDeEmph[i] =
+				config->usb3_ports[i].tx_de_emp;
+		}
+		if (config->usb3_ports[i].tx_downscale_amp) {
+			params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
+			params->Usb3HsioTxDownscaleAmp[i] =
+				config->usb3_ports[i].tx_downscale_amp;
+		}
+	}
+
+	/* Enable xDCI controller if enabled in devicetree and allowed */
+	dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+	if (!xdci_can_enable())
+		dev->enabled = 0;
+	params->XdciEnable = dev->enabled;
+
+	/* PCI Express */
+	for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
+		if (config->PcieClkSrcUsage[i] == 0)
+			config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
+	}
+	memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
+	       sizeof(config->PcieClkSrcUsage));
+	memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+	       sizeof(config->PcieClkSrcClkReq));
+
+	/* eMMC and SD */
+	dev = dev_find_slot(0, PCH_DEVFN_EMMC);
+	if (!dev)
+		params->ScsEmmcEnabled = 0;
+	else {
+		params->ScsEmmcEnabled = dev->enabled;
+		params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+		params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
+		if (config->EmmcHs400DllNeed == 1) {
+			params->PchScsEmmcHs400RxStrobeDll1 =
+				config->EmmcHs400RxStrobeDll1;
+			params->PchScsEmmcHs400TxDataDll =
+				config->EmmcHs400TxDataDll;
+		}
+	}
+
+	dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
+	if (!dev)
+		params->ScsSdCardEnabled = 0;
+	else
+		params->ScsSdCardEnabled = dev->enabled;
+
+	dev = dev_find_slot(0, PCH_DEVFN_UFS);
+	if (!dev)
+		params->ScsUfsEnabled = 0;
+	else
+		params->ScsUfsEnabled = dev->enabled;
+
+	params->Heci3Enabled = config->Heci3Enabled;
+	params->Device4Enable = config->Device4Enable;
+	params->SkipMpInit = !chip_get_fsp_mp_init();
+
+	/* VrConfig Settings for 5 domains
+	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
+	 * 3 = GT unsliced,  4 = GT sliced */
+	for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
+		fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
+
+	/* Vt-D config */
+	tconfig->VtdDisable = config->VtdDisable;
+}
+
+/* Mainboard GPIO Configuration */
+__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc
index 99bc25f20e..c3bfdbbf33 100644
--- a/src/soc/intel/cannonlake/romstage/Makefile.inc
+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc
@@ -15,4 +15,5 @@
 
 romstage-y += power_state.c
 romstage-y += romstage.c
+romstage-y += fsp_params.c
 romstage-y += systemagent.c
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
new file mode 100644
index 0000000000..b8cddbf542
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <chip.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
+{
+	unsigned int i;
+	uint32_t mask = 0;
+
+	/* Set IGD stolen size to 64MB. */
+	m_cfg->IgdDvmt50PreAlloc = 2;
+	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
+	m_cfg->SaGv = config->SaGv;
+	m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
+	m_cfg->RMT = config->RMT;
+
+	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
+		if (config->PcieRpEnable[i])
+			mask |= (1 << i);
+	}
+	m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PrmrrSize = config->PrmrrSize;
+	m_cfg->EnableC6Dram = config->enable_c6dram;
+	/* Disable Cpu Ratio Override temporary. */
+	m_cfg->CpuRatio = 0;
+	m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
+	/* Disable Vmx if Vt-d is already disabled */
+	if (config->VtdDisable)
+		m_cfg->VmxEnable = 0;
+	else
+		m_cfg->VmxEnable = config->VmxEnable;
+#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
+	m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
+#endif
+}
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	assert(dev != NULL);
+	const config_t *config = dev->chip_info;
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	soc_memory_init_params(m_cfg, config);
+
+	/* Enable SMBus controller based on config */
+	m_cfg->SmbusEnable = config->SmbusEnable;
+	/* Set debug probe type */
+	m_cfg->PlatformDebugConsent = config->DebugConsent;
+
+	mainboard_memory_init_params(mupd);
+}
+
+__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 8bdabbf803..6f610b6eec 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -147,58 +147,3 @@ asmlinkage void car_stage_entry(void)
 
 	run_postcar_phase(&pcf);
 }
-
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
-{
-	unsigned int i;
-	uint32_t mask = 0;
-
-	/* Set IGD stolen size to 64MB. */
-	m_cfg->IgdDvmt50PreAlloc = 2;
-	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
-	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
-	m_cfg->SaGv = config->SaGv;
-	m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
-	m_cfg->RMT = config->RMT;
-
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
-			mask |= (1 << i);
-	}
-	m_cfg->PcieRpEnableMask = mask;
-	m_cfg->PrmrrSize = config->PrmrrSize;
-	m_cfg->EnableC6Dram = config->enable_c6dram;
-	/* Disable Cpu Ratio Override temporary. */
-	m_cfg->CpuRatio = 0;
-	m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
-	/* Disable Vmx if Vt-d is already disabled */
-	if (config->VtdDisable)
-		m_cfg->VmxEnable = 0;
-	else
-		m_cfg->VmxEnable = config->VmxEnable;
-#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
-	m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
-#endif
-}
-
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-{
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
-	assert(dev != NULL);
-	const config_t *config = dev->chip_info;
-	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-
-	soc_memory_init_params(m_cfg, config);
-
-	/* Enable SMBus controller based on config */
-	m_cfg->SmbusEnable = config->SmbusEnable;
-	/* Set debug probe type */
-	m_cfg->PlatformDebugConsent = config->DebugConsent;
-
-	mainboard_memory_init_params(mupd);
-}
-
-__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
-{
-	/* Do nothing */
-}