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authorMichael Niewöhner <foss@mniewoehner.de>2019-10-08 00:30:38 +0200
committerNico Huber <nico.h@gmx.de>2019-10-26 15:47:34 +0000
commit7ef19036fbfeaad63ccb4dde26b3133d6128d0b8 (patch)
treeaadb0535e72c94dfc5f359abc37d06acb3c91298 /src/soc/intel
parentfa62e01b902c00144847103113902c3c817c2443 (diff)
downloadcoreboot-7ef19036fbfeaad63ccb4dde26b3133d6128d0b8.tar.xz
soc/intel/skylake: move/rename files after drop of FSP 1.1
Follow-up commit where only files are moved and paths adapted to make review of the previous commit easier. Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35868 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/Makefile.inc3
-rw-r--r--src/soc/intel/skylake/chip.c (renamed from src/soc/intel/skylake/chip_fsp20.c)0
-rw-r--r--src/soc/intel/skylake/include/soc/ramstage.h (renamed from src/soc/intel/skylake/include/fsp20/soc/ramstage.h)2
-rw-r--r--src/soc/intel/skylake/include/soc/romstage.h (renamed from src/soc/intel/skylake/include/fsp20/soc/romstage.h)0
-rw-r--r--src/soc/intel/skylake/romstage/Makefile.inc2
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c (renamed from src/soc/intel/skylake/romstage/romstage_fsp20.c)0
6 files changed, 3 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 8174765210..cb0906c1d5 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -42,7 +42,7 @@ romstage-y += spi.c
romstage-y += uart.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
-ramstage-y += chip_fsp20.c
+ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += elog.c
ramstage-y += finalize.c
@@ -100,7 +100,6 @@ endif
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
-CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
# Currently used for microcode path.
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip.c
index c4f4e50cd2..c4f4e50cd2 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip.c
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h
index e5660a6f66..4157c4e09b 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/soc/ramstage.h
@@ -21,7 +21,7 @@
#include <fsp/api.h>
#include <fsp/util.h>
-#include "../../../chip.h"
+#include "../../chip.h"
#define FSP_SIL_UPD FSP_S_CONFIG
#define FSP_MEM_UPD FSP_M_CONFIG
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index 364bf52529..364bf52529 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 7bd1c6fb97..dff89ce2dc 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,3 +1,3 @@
romstage-y += ../../../../cpu/intel/car/romstage.c
-romstage-y += romstage_fsp20.c
+romstage-y += romstage.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage.c
index af89441194..af89441194 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage.c