diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-26 00:17:52 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-13 13:17:31 +0000 |
| commit | a0426267e330c60aa74528a06a0e130efe2ad32f (patch) | |
| tree | 0758cce1d8739e398a41e351c89b1f31db26e73f /src/soc/intel | |
| parent | a472e33634b7c9709fccb3c60d1d21b2c75e1347 (diff) | |
| download | coreboot-a0426267e330c60aa74528a06a0e130efe2ad32f.tar.xz | |
broadwell: Flatten `acpi_init_gnvs` function
Instead of relying on mainboards to call it, do like Lynx Point.
Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46793
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/broadwell/acpi.c | 25 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pch/lpc.c | 25 |
2 files changed, 25 insertions, 25 deletions
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 3d5e74ae5c..7366642c62 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -148,31 +148,6 @@ static int get_cores_per_package(void) return cores; } -void acpi_init_gnvs(struct global_nvs *gnvs) -{ - /* Set unknown wake source */ - gnvs->pm1i = -1; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 2111913a0e..73b83e4e09 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -13,6 +13,8 @@ #include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <cbmem.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> #include <string.h> #include <soc/gpio.h> #include <soc/iobp.h> @@ -621,6 +623,29 @@ static void southcluster_inject_dsdt(const struct device *device) if (gnvs) { acpi_create_gnvs(gnvs); + + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + +#if CONFIG(CONSOLE_CBMEM) + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + } + /* And tell SMI about it */ apm_control(APM_CNT_GNVS_UPDATE); |