diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-02-27 15:54:56 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-03 10:18:17 +0000 |
| commit | b3fa6a03a895ee43e9679d5c6608e98d1eec6e67 (patch) | |
| tree | 30aceaed112f8b39309f90cfc4977850ae2f1802 /src/soc/intel | |
| parent | d615230cced8238029d579411d8ee69f68c7ec5f (diff) | |
| download | coreboot-b3fa6a03a895ee43e9679d5c6608e98d1eec6e67.tar.xz | |
soc/intel/tigerlake: configure ethernet
Configure ethernet based on board config
BUG=none
BRANCH=none
TEST= build TGLRVP and check ethernet is disabled based on devicetree
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39153
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params_tgl.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index d22cde021c..fbc9f23083 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* LAN */ + dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + if (!dev) + params->PchLanEnable = 0; + else + params->PchLanEnable = dev->enabled; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; |