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| author | Martin Roth <martin.roth@se-eng.com> | 2014-06-11 09:35:37 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-06-13 18:34:04 +0200 |
| commit | d866e5872d5570fded81a4d392884725009a17dd (patch) | |
| tree | 992ba3c0c397df55e37b2e9447f9631f754887e9 /src/soc/intel | |
| parent | 4dfc50b8773a2ddc3f87f9e6d988de1d8751ba53 (diff) | |
| download | coreboot-d866e5872d5570fded81a4d392884725009a17dd.tar.xz | |
fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOT
While pushing the fsp_baytrail code, it was requested that we change
CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT.
These were missed in the change.
Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5972
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 87fe5aec50..60a1f7af7e 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -314,7 +314,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, pFspInitParams->NvsBufferPtr = NULL; pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; -#if IS_ENABLED(CONFIG_ENABLE_FAST_BOOT) +#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif |