diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-27 20:50:08 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-28 01:35:43 +0000 |
| commit | e5cecd0ea42b52ac59cb75abe1bdcc83f391e9bf (patch) | |
| tree | 4402c38587bcbfc179dfa0db5f8c1df14301dbc8 /src/soc/intel | |
| parent | c3e4f6344dfec53c0ac5a07632270816a30046b9 (diff) | |
| download | coreboot-e5cecd0ea42b52ac59cb75abe1bdcc83f391e9bf.tar.xz | |
soc/intel/skylake: Fix FSP1.1 booting issue with HW based dram top calculation
This patch ensures skylake device using FSP1.1 can use HW based
DRAM top calculation which was broken due to skylake fsp1.1 not
honoring any UPD to know PRMMR size and default reserving 1MB for PRMRR size.
This WA is not needed for FSP2.0 implementation due to
PrmrrSize UPD is available and considering into hw based dram top
calculation.
BRANCH=none
BUG=b:63974384
TEST=Build and boot lars which is using skylake 1.1 fsp.
Change-Id: Iade0d2cb2a290fc4c9f0e6b1eaadc8afff2fa581
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/memmap.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index d5d372484c..1ccaf1d3b8 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -178,7 +178,10 @@ static u32 calculate_dram_base(void) dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)); config = dev->chip_info; - prmrr_size = config->PrmrrSize; + if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) + prmrr_size = 1*MiB; + else + prmrr_size = config->PrmrrSize; if (prmrr_size > 0) { /* |