diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-06-06 23:56:18 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-09 16:57:13 +0200 |
| commit | f05d2e17b069a1955ee858e77e8f9abfd62d3ff9 (patch) | |
| tree | 5285f2993f65c53bd6fdecd093d5b1ae637c8ceb /src/soc/intel | |
| parent | 930577ac7b090e9af0a988560c3445b7ba78f08c (diff) | |
| download | coreboot-f05d2e17b069a1955ee858e77e8f9abfd62d3ff9.tar.xz | |
soc/baytrail: fix ACPI table by recollecting TOLM
Adapted from Chromium commit 8fbe1e7 for soc/braswell
(also review.coreboot.org/#/c/20060/); same issue affects
baytrail as well.
This patch recollects TOLM accessing; as Aaron recalled some
core_msr_script turns off access to TOLM register, he suggests
to store tolm to avoid getting back a zero while setting acpi
nvs space.
Change-Id: Ib26d4fe229b3f7d8ee664f5d89774d1f4a997f51
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/baytrail/northcluster.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 55ace5911d..c8ba9c15ff 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -20,7 +20,7 @@ #include <device/pci_ids.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/acpi.h> - +#include <stddef.h> #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/pci_devs.h> @@ -65,7 +65,14 @@ uint32_t nc_read_top_of_low_memory(void) { - return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); + MAYBE_STATIC uint32_t tolm = 0; + + if (tolm) + return tolm; + + tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); + + return tolm; } static void nc_read_resources(device_t dev) |