summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-08-30 18:04:02 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-09-02 08:36:06 +0000
commit03ddd190fd6a2e91b16e6fd8a101cf4e11d7cd7b (patch)
tree0bed4ff346fd9ded528f89cc367fdff38e3f9cd3 /src/soc/intel
parent539b97df62bafa5bf526ee5882c01a8cf928f79d (diff)
downloadcoreboot-03ddd190fd6a2e91b16e6fd8a101cf4e11d7cd7b.tar.xz
soc/intel/skylake: enable GMM in devicetree
Enables Gaussian Mixture Model (GMM) only if the corresponding pci device is enabled in the device tree Tested on Asrock H110M DVS motherboard Change-Id: I21409adf85b70bccc30dd8e12a03ad7921544b3c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c4
-rw-r--r--src/soc/intel/skylake/include/soc/pci_devs.h3
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 064f71e2f2..85d3edf330 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -441,6 +441,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev->enabled = 0;
params->XdciEnable = dev->enabled;
+ /* Enable or disable Gaussian Mixture Model in devicetree */
+ dev = pcidev_path_on_root(SA_DEVFN_GMM);
+ params->GmmEnable = dev ? dev->enabled : 0;
+
/*
* Send VR specific mailbox commands:
* 000b - no VR specific command sent
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 0e8bb6841f..ff6b8c1c23 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -42,6 +42,9 @@
#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
+#define SA_DEV_SLOT_GMM 0x08
+#define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0)
+#define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_GMM, 0)
/* PCH Devices */
#define PCH_DEV_SLOT_ISH 0x13