summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorJett Rink <jettrink@chromium.org>2019-02-27 13:58:05 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-03-04 14:01:38 +0000
commit088d2a3dad5cb79d651c815476c110d4cf6a48fb (patch)
tree9ff5a8d74dfc3a0a5260523330f9f39b854fa7d3 /src/soc/intel
parent59e5c80237f76dfb5dff9b751aa23f30ef54a3af (diff)
downloadcoreboot-088d2a3dad5cb79d651c815476c110d4cf6a48fb.tar.xz
soc/intel/cnl/acpi: add ish ACPI device
Create the ISH ACPI device so we can hang fields off of a _DSD table. Since this is also a PCI device that has run time probing, we can always emit the ACPI device and let the device tree turn the device on or off. BRANCH=none BUG=b:122722008 TEST=verify that _DSD table gets publish under ISH device in kernel ACPI tables. Also verified that device is still turned off if device tree for ISH is off. Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/31681 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/acpi/ish.asl22
-rw-r--r--src/soc/intel/cannonlake/acpi/southbridge.asl3
2 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/ish.asl b/src/soc/intel/cannonlake/acpi/ish.asl
new file mode 100644
index 0000000000..1c832b4ea9
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/ish.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Integrated Sensor Hub Controller 0:13.0 */
+
+Device (ISHB)
+{
+ Name (_ADR, 0x00130000)
+ Name (_DDN, "Integrated Sensor Hub Controller")
+}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index dfa29751a6..ae8de6a1df 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -51,6 +51,9 @@
/* SMBus 0:1f.4 */
#include "smbus.asl"
+/* ISH 0:13.0 */
+#include "ish.asl"
+
/* USB XHCI 0:14.0 */
#include "xhci.asl"