summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorShelley Chen <shchen@chromium.org>2018-02-07 17:29:19 -0800
committerMartin Roth <martinroth@google.com>2018-02-11 00:00:07 +0000
commit106a9fe882f329cb3dbafc56601557b1d35ac672 (patch)
tree92b8f829709d6b3cdf02067e6cbf3eed69301cde /src/soc/intel
parentf0b3a5fe4fca88cc17933ff18bec483afcf28002 (diff)
downloadcoreboot-106a9fe882f329cb3dbafc56601557b1d35ac672.tar.xz
mb/google/fizz: Set SATA GPIOs in bootblock
Previously, we were seeing device boot into the recovery screen with error code 0x5a. This was root caused to the SATA GPIOs (specifically DEVSLP) not being initialized early enough, causing the SATA 1 link detection to time out and the device to reboot into recovery with 0x5a instead of booting into the OS as usual. BUG=b:69715162 BRANCH=None TEST=after flashing BIOS, set gbb flags to 0, then type reboot from the OS. Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions