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authorRonak Kanabar <ronak.kanabar@intel.com>2020-04-27 20:48:09 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-12 20:06:52 +0000
commit194695fd953a2a8bd10eedc9aa7811c338988d3d (patch)
tree7038206fc01b8cef9c8c38603c7640f86f06ffb5 /src/soc/intel
parent7f9bca73286c393a919112133d50a767500cfa95 (diff)
downloadcoreboot-194695fd953a2a8bd10eedc9aa7811c338988d3d.tar.xz
soc/intel/jasperlake: Remove deprecated UPDs
IedSize and EnableC6Dram are removed in JSL FSP v2114 so remove them from 'fsp_params.c'. BUG=155054804 BRANCH=None TEST=Build and boot JSLRVP Change-Id: I47bd3f87bdb59625098c0d734695f02d738f8bbd Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41239 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/jasperlake/romstage/fsp_params.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index 1393c44eed..d9063b0b0c 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -26,7 +26,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
}
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
- m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
m_cfg->SaGv = config->SaGv;
m_cfg->RMT = config->RMT;
@@ -49,7 +48,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
sizeof(config->PcieClkSrcClkReq));
m_cfg->PrmrrSize = config->PrmrrSize;
- m_cfg->EnableC6Dram = config->enable_c6dram;
/* Disable BIOS Guard */
m_cfg->BiosGuard = 0;