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authorAaron Durbin <adurbin@chromium.org>2013-10-30 17:08:59 -0500
committerAaron Durbin <adurbin@google.com>2014-03-11 19:53:17 +0100
commit1eae3eed293b0e781efec68840eb80749baa5ede (patch)
tree712331810102e1d0c1f8a8b6084258cc0db42ade /src/soc/intel
parent223d4a4ff67ab6212c2dced57b29a078ba82375b (diff)
downloadcoreboot-1eae3eed293b0e781efec68840eb80749baa5ede.tar.xz
baytrail: allow function disable on TXE
Previously it was not known how to put the TXE pci device into D3Hot. It's been disseminated that this is not a requirement for disabling the TXE pci device in the function disable register. Therefore, allow this by returning 0 from place_device_in_d3hot(). BUG=chrome-os-partner:22871 BRANCH=None TEST=Temporarily set TXE to be disabled. Noted FUNC_DIS was being set accordingly. Change-Id: Ibf537bf8ba718859591dc89bdf41e57c1ea9d836 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175490 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4925 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/baytrail/southcluster.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index eacabf3098..42349fac4e 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -322,7 +322,8 @@ static int place_device_in_d3hot(device_t dev)
offset = 0x50;
break;
case PCI_DEVFN(TXE_DEV, TXE_FUNC):
- break;
+ /* TXE cannot be placed in D3Hot. */
+ return 0;
case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC):
offset = 0xa0;
break;