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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-10-09 20:33:16 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-11-02 03:20:50 +0000 |
| commit | 23012a0dff9810c9055369fb5f21e8ef5f074f7b (patch) | |
| tree | 948b982d6f2ebbabeb0233d92cd2822b6b224b12 /src/soc/intel | |
| parent | 49e0510d57e47e8b6013afd6699d87bd4da9a693 (diff) | |
| download | coreboot-23012a0dff9810c9055369fb5f21e8ef5f074f7b.tar.xz | |
soc/intel/icelake: Allow coreboot to reserve stack for fsp
Change-Id: I5f2d9548b8e2c7b1d154b7bad126ec7b1052231a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/icelake/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 664add2c8c..c4ee841802 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_USES_CB_STACK select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -89,6 +90,7 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex + default 0x20000 if FSP_USES_CB_STACK default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and |