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| author | Keith Short <keithshort@chromium.org> | 2019-05-16 14:08:31 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-05-22 16:54:46 +0000 |
| commit | 24302633a558e545efcc84178136bd1879f6d8ee (patch) | |
| tree | d1ae419a5796ffb570b9862e60884b2b9d975c1b /src/soc/intel | |
| parent | bb41aba0d8c3c3cbfee44b0f7267e78fb7d012ee (diff) | |
| download | coreboot-24302633a558e545efcc84178136bd1879f6d8ee.tar.xz | |
post_code: add post code for memory error
Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails
to initialize RAM.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions