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authorShawn Nematbakhsh <shawnn@chromium.org>2015-08-25 18:03:31 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-09 20:18:23 +0000
commit3bad4cb086276a0fef715a3e661b489c59e27e08 (patch)
tree4b8c9e2976c550439549d200d86187ad4d446035 /src/soc/intel
parentf966d3b3ae7c52691cfc5697c784c7e99f7d2fff (diff)
downloadcoreboot-3bad4cb086276a0fef715a3e661b489c59e27e08.tar.xz
braswell: acpi: Allow DPTF thresholds to be defined at board-level
Similar to Skylake, allow braswell mainboards to override the default DPTF thresholds. BUG=chrome-os-partner:43884 TEST=Build for Strago BRANCH=Strago Change-Id: Id2574e98c444b8bf4da8ca36f3eeeb06568e78e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 799a7006e8fcacfea8e8e0de5c99c3ce3c4ac34f Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: If69627163237674a28fb8a26b4ce1886e5dbfc17 Original-Reviewed-on: https://chromium-review.googlesource.com/296033 Original-Commit-Ready: Shawn N <shawnn@chromium.org> Original-Tested-by: Shawn N <shawnn@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/braswell/acpi/cpu.asl11
-rw-r--r--src/soc/intel/braswell/acpi/dptf/cpu.asl63
2 files changed, 49 insertions, 25 deletions
diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl
index 0ae51f2002..c9cb83b915 100644
--- a/src/soc/intel/braswell/acpi/cpu.asl
+++ b/src/soc/intel/braswell/acpi/cpu.asl
@@ -18,17 +18,6 @@
* Foundation, Inc.
*/
-/* CPU */
-#define DPTF_CPU_PASSIVE 80
-#define DPTF_CPU_CRITICAL 90
-#define DPTF_CPU_PASSIVE 80
-#define DPTF_CPU_CRITICAL 90
-#define DPTF_CPU_ACTIVE_AC0 90
-#define DPTF_CPU_ACTIVE_AC1 80
-#define DPTF_CPU_ACTIVE_AC2 70
-#define DPTF_CPU_ACTIVE_AC3 60
-#define DPTF_CPU_ACTIVE_AC4 50
-
/* These devices are created at runtime */
External (\_PR.CP00, DeviceObj)
External (\_PR.CP01, DeviceObj)
diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl
index 018144c3e1..3e51c29d7d 100644
--- a/src/soc/intel/braswell/acpi/dptf/cpu.asl
+++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl
@@ -1,3 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef DPTF_CPU_PASSIVE
+#define DPTF_CPU_PASSIVE 80
+#endif
+
+#ifndef DPTF_CPU_CRITICAL
+#define DPTF_CPU_CRITICAL 90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC0
+#define DPTF_CPU_ACTIVE_AC0 90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC1
+#define DPTF_CPU_ACTIVE_AC1 80
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC2
+#define DPTF_CPU_ACTIVE_AC2 70
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC3
+#define DPTF_CPU_ACTIVE_AC3 60
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC4
+#define DPTF_CPU_ACTIVE_AC4 50
+#endif
+
External (\_PR.CP00._TSS, MethodObj)
External (\_PR.CP00._TPC, MethodObj)
External (\_PR.CP00._PTC, PkgObj)
@@ -127,52 +175,39 @@ Device (B0DB)
{
Return (\_SB.MPPC)
}
-#ifdef DPTF_CPU_CRITICAL
+
Method (_CRT)
{
Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL))
}
-#endif
-#ifdef DPTF_CPU_PASSIVE
Method (_PSV)
{
Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE))
}
-#endif
-#ifdef DPTF_CPU_ACTIVE_AC0
Method (_AC0)
{
Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0))
}
-#endif
-#ifdef DPTF_CPU_ACTIVE_AC1
Method (_AC1)
{
Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1))
}
-#endif
-#ifdef DPTF_CPU_ACTIVE_AC2
Method (_AC2)
{
Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2))
}
-#endif
-#ifdef DPTF_CPU_ACTIVE_AC3
Method (_AC3)
{
Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3))
}
-#endif
-#ifdef DPTF_CPU_ACTIVE_AC4
Method (_AC4)
{
Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4))
}
-#endif
}