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authorSubrata Banik <subrata.banik@intel.com>2019-04-12 14:39:42 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-04-16 02:14:38 +0000
commit41dad286d846819242a84fc65faed2bbb35845ac (patch)
treea3fc3a3202afb340cde6475a473cc19876d25eb9 /src/soc/intel
parent79f92910ebb1a281b87cd2586cff9c5d06478d6c (diff)
downloadcoreboot-41dad286d846819242a84fc65faed2bbb35845ac.tar.xz
soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML
This patch performs MP initialization by FSP using coreboot MP PPI service. BUG=b:74436746 TEST=Able to perform MP initialization on WHL and CML platform. Change-Id: I530d50e5aacc3cb9b625df14a50d4c5923e3fb4d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/Kconfig8
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c5
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c5
3 files changed, 17 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index c30b562db9..14404f7589 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -27,6 +27,8 @@ config SOC_INTEL_WHISKEYLAKE
bool
default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE
+ select FSP_PEIM_TO_PEIM_INTERFACE
+ select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
help
Intel Whiskeylake support
@@ -34,6 +36,12 @@ config SOC_INTEL_COMETLAKE
bool
default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE
+ # TODO:
+ # Delete FSP_PEIM_TO_PEIM_INTERFACE and
+ # USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selection
+ # and select PLATFORM_USES_FSP2_1 once FSP support for CML is ready
+ select FSP_PEIM_TO_PEIM_INTERFACE
+ select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
help
Intel Cometlake support
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index b8dba184cb..1fd42cda17 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -18,7 +18,9 @@
#include <device/device.h>
#include <device/pci.h>
#include <fsp/api.h>
+#include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h>
+#include <intelblocks/mp_init.h>
#include <intelblocks/xdci.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
@@ -142,6 +144,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Usb3OverCurrentPin[i] = 0;
}
+ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
+ params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+
mainboard_silicon_init_params(params);
/* Set PsysPmax if it is available from DT */
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index ffdcee47e9..4545f52696 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -68,7 +68,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->VmxEnable = config->VmxEnable;
#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
- m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
+ m_cfg->SkipMpInit = 0;
+ else
+ m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
#endif
/* Set CpuRatio to match existing MSR value */