diff options
| author | Krzysztof Sywula <krzysztof.m.sywula@intel.com> | 2019-03-13 16:48:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-22 12:24:16 +0000 |
| commit | 42a66fb721fb512a9b2e274303a6a4cb9311dfab (patch) | |
| tree | c0cd410cfb7e4b5fdcb211572fae6e1eff045043 /src/soc/intel | |
| parent | f71792f8c91ea7b254ed7f478253ef2bec7819ff (diff) | |
| download | coreboot-42a66fb721fb512a9b2e274303a6a4cb9311dfab.tar.xz | |
soc/intel/cannonlake: Enable power button smi in pre-OS
This change enables user to shutdown the system by shortly pressing
power button (<10sec) before OS is loaded. Main use case is shutdown
from recovery/broken screen.
BUG=N/A
TEST=Boot up into recovery screen on Sarien platform, press power button
once, and system should shutdown immediatelly.
Change-Id: I7655daf65ff058df7d9bad4567f74b4f4007acb4
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/pmc.c | 15 |
2 files changed, 16 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 6bedb81390..7c06d25fd7 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -456,7 +456,7 @@ static void post_mp_init(void) * Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - smm_southbridge_enable(PWRBTN_EN | GBL_EN); + smm_southbridge_enable(GBL_EN); /* Lock down the SMRAM space. */ smm_lock(); diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 931c4af89b..5cd31f9f97 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -62,6 +62,21 @@ void pmc_soc_restore_power_failure(void) pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE); } +static void pm1_enable_pwrbtn_smi(void *unused) +{ + /* + * Enable power button SMI only before jumping to payload. This ensures + * that: + * 1. Power button SMI is enabled only after coreboot is done. + * 2. On resume path, power button SMI is not enabled and thus avoids + * any shutdowns because of power button presses due to power button + * press in resume path. + */ + pmc_update_pm1_enable(PWRBTN_EN); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); + static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) { uint32_t reg; |